29.16.7 PMC PLL Analog Control Register

This register must be loaded with the recommended values described in the Electrical Characteristics section.

All fields defined here are applied to the PLL defined by the last ID field written in the PMC_PLL_UPDT register.

Name: PMC_PLL_ACR
Offset: 0x0018
Reset: 0x00020033
Property: Read/Write

Bit 3130292827262524 
   LOOP_FILTER[5:0] 
Access R/WR/WR/WR/WR/WR/W 
Reset 000000 
Bit 2322212019181716 
      LOCK_THR[2:0] 
Access R/WR/WR/W 
Reset 010 
Bit 15141312111098 
   UTMIBGUTMIVRCONTROL[11:8] 
Access R/WR/WR/WR/WR/WR/W 
Reset 000000 
Bit 76543210 
 CONTROL[7:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00110011 

Bits 29:24 – LOOP_FILTER[5:0] Loop Filter Selection

Bits 18:16 – LOCK_THR[2:0] PLL Lock Threshold Value Selection

Bit 13 – UTMIBG UPLL Bandgap Control

This bit has no effect when applied to PLLA.
ValueDescription
0 The UPLL bandgap is switched off.
1 The UPLL bandgap is switched on.

Bit 12 – UTMIVR UPLL Voltage Regulator Control

This bit has no effect when applied to PLLA.
ValueDescription
0 The UPLL voltage regulator is switched off.
1 The UPLL voltage regulator is switched on.

Bits 11:0 – CONTROL[11:0] PLL CONTROL Value Selection

On PLLA, this field controls the DCO analog filters:
Field Description
CONTROL[1:0] Analog VCO filter selection
CONTROL[4:2] Process configuration
CONTROL[6:5] VCO gain configuration
CONTROL[7] Offset frequency adjustment
CONTROL[8] External pad connection
CONTROL[9] Test mode dedicated
CONTROL[10] DAC mode
CONTROL[11] Enable output phases
On UPLL, this field controls the following PLL ports:
Field Description
CONTROL[1:0] Not used
CONTROL[4:2] Process configuration
CONTROL[6:5] VCO gain configuration
CONTROL[7] Offset frequency adjustment
CONTROL[11:8] Not used