33.7.6 SDRAMC Interrupt Disable Register
This register can only be
written if the WPITEN bit is cleared in the SDRAMC Write Protection Mode Register.
The following configuration values are valid for all listed bit names of this register:
0: No effect.
1: Disables the corresponding interrupt.
| Name: | SDRAMC_IDR |
| Offset: | 0x18 |
| Reset: | – |
| Property: | Write-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| | | | | | | | | | |
| Access | | | | | | | | | |
| Reset | | | | | | | | | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| | | | | | | | | | |
| Access | | | | | | | | | |
| Reset | | | | | | | | | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| | | | | | | | | | |
| Access | | | | | | | | | |
| Reset | | | | | | | | | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| | | | | | | | SECE | RES | |
| Access | | | | | | | W | W | |
| Reset | | | | | | | – | – | |
Bit 1 – SECE Security and/or
Safety Event Interrupt Disable
Bit 0 – RES Refresh Error Interrupt Disable
