33.7.10 SDRAMC Configuration Register 1
This register can only be written if the WPEN bit is cleared in the SDRAMC Write Protection Mode Register.
| Name: | SDRAMC_CFR1 |
| Offset: | 0x28 |
| Reset: | 0x00000002 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| CMD_MUX | ADD_DATA_MUX | UNAL | |||||||
| Access | R/W | R/W | R/W | ||||||
| Reset | 0 | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| TMRD[3:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 1 | 0 | |||||
Bit 11 – CMD_MUX Commands are Multiplexed with Address and Data
To use this feature, ADD_DATA_MUX must be set to ‘1’. This feature allows to reduce the number of pins.
| Value | Name | Description |
|---|---|---|
| 0 | UNSUPPORTED | Commands are not multiplexed with address and data. |
| 1 | SUPPORTED | Commands are multiplexed with address and data. |
Bit 10 – ADD_DATA_MUX Multiplexed Address and Data
.This feature allows to reduce the number of pins.
| Value | Name | Description |
|---|---|---|
| 0 | UNSUPPORTED | Data and address are not multiplexed |
| 1 | SUPPORTED | Data and address are multiplexed |
Bit 8 – UNAL Always written to 1
This bit must be always written to 1.
Bits 3:0 – TMRD[3:0] Load Mode Register Command to Active or Refresh Command
This field defines the delay between a “Load Mode Register” command and an active or refresh command in number of cycles. Number of cycles is between 0 and 15.