33.7.9 SDRAMC Memory Device Register
This register can only be written if the WPEN bit is cleared in the SDRAMC Write Protection Mode Register.
| Name: | SDRAMC_MDR |
| Offset: | 0x24 |
| Reset: | 0x00000000 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| SHIFT_SAMPLING[1:0] | MD[1:0] | ||||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 | |||||
Bits 5:4 – SHIFT_SAMPLING[1:0] Shift Sampling Point of Data
Shifts the sampling point of data coming from the memory device. The higher the memory device clock frequency, the higher the SHIFT_SAMPLING value. Refer to the section "Electrical Characteristics".
| Value | Name | Description |
|---|---|---|
| 0 | – | Reserved. |
| 1 | SHIFT_ONE_CYCLE | Sampling point is shifted by one cycle. |
| 2 | SHIFT_TWO_CYCLES | Sampling point is shifted by two cycles. |
| 3 | SHIFT_THREE_CYCLES | Sampling point is shifted by three cycles. |
Bits 1:0 – MD[1:0] Memory Device Type
| Value | Name | Description |
|---|---|---|
| 0 | SDRAM | SDRAM |
| 1 | LPSDRAM | Low-power SDRAM |
| 2 | – | Reserved |
| 3 | – | Reserved |