33.7.11 SDRAMC OCMS Register
This register can only be written if the WPEN bit is cleared in the SDRAMC Write Protection Mode Register.
| Name: | SDRAMC_OCMS |
| Offset: | 0x2C |
| Reset: | 0x00000000 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| TAMPCLR | SDR_SE | ||||||||
| Access | R/W | R/W | |||||||
| Reset | 0 | 0 |
Bit 4 – TAMPCLR Tamper Clear Enable
| Value | Description |
|---|---|
| 0 | A tamper detection event has no effect on SDRAMC scrambling keys. |
| 1 | A tamper detection event immediately clears SDRAMC scrambling keys. |
Bit 0 – SDR_SE SDRAM Memory Controller Scrambling Enable
| Value | Description |
|---|---|
| 0 |
Disables off-chip scrambling for SDR-SDRAM access. |
| 1 |
Enables off-chip scrambling for SDR-SDRAM access. |