33.7.4 SDRAMC Low-Power Register


Bit	31	30	29	28	27	26	25	24

Access
Reset


Bit	23	22	21	20	19	18	17	16
								SELFDONE
Access								R/W
Reset								0


Bit	15	14	13	12	11	10	9	8
		SELFAUTO	TIMEOUT[1:0]		DS[1:0]		TCSR[1:0]
Access		R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset		0	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
		PASR[2:0]					LPCB[1:0]
Access		R/W	R/W	R/W			R/W	R/W
Reset		0	0	0			0	0

Bit 16 – SELFDONE Self-refresh Done (read-only)

This bit indicates that the external device is in Self-refresh mode.

Bit 14 – SELFAUTO Self-refresh Exit Autorefresh

Value	Description
1	Upon exiting Self-refresh mode, autorefresh command is immediately performed after t_XSR.
0	Upon exiting Self-refresh mode, active command is immediately performed after t_XSR. The autorefresh command is issued every 15.6 μs or less.

Bits 13:12 – TIMEOUT[1:0] Time to Define When Low-power Mode Is Enabled

Value	Name	Description
0	LP_LAST_XFER	The SDRAMC activates the SDRAM Low-power mode immediately after the end of the last transfer.
1	LP_LAST_XFER_64	The SDRAMC activates the SDRAM Low-power mode 64 clock cycles after the end of the last transfer.
2	LP_LAST_XFER_128	The SDRAMC activates the SDRAM Low-power mode 128 clock cycles after the end of the last transfer.
3	Reserved

Bits 11:10 – DS[1:0] Drive Strength (only for low-power SDRAM)

DS is transmitted to the SDRAM during initialization to select the SDRAM strength of data output. This parameter must be set according to the SDRAM device specification.

After initialization, as soon as the DS field is modified and Self-refresh mode is activated, the Extended Mode Register is accessed automatically and DS bits are updated before entry in Self-refresh mode. This feature is not supported when SDRAMC shares an external bus with another controller.

Bits 9:8 – TCSR[1:0] Temperature Compensated Self-Refresh (only for low-power SDRAM)

TCSR is transmitted to the SDRAM during initialization to set the refresh interval during Self-refresh mode depending on the temperature of the low-power SDRAM. This parameter must be set according to the SDRAM device specification.

After initialization, as soon as the TCSR field is modified and Self-refresh mode is activated, the Extended Mode Register is accessed automatically and TCSR bits are updated before entry in Self-refresh mode. This feature is not supported when SDRAMC shares an external bus with another controller.

Bits 6:4 – PASR[2:0] Partial Array Self-refresh (only for low-power SDRAM)

PASR is transmitted to the SDRAM during initialization to specify whether only one quarter, one half or all banks of the SDRAM array are enabled. Disabled banks are not refreshed in Self-refresh mode. This parameter must be set according to the SDRAM device specification.

After initialization, as soon as the PASR field is modified and Self-refresh mode is activated, the Extended Mode Register is accessed automatically and PASR bits are updated before entry in Self-refresh mode. This feature is not supported when SDRAMC shares an external bus with another controller.

Bits 1:0 – LPCB[1:0] Low-power Configuration Bits

Value	Name	Description
0	DISABLED	The low-power feature is inhibited: no Powerdown, Self-refresh or Deep Powerdown command is issued to the SDRAM device.
1	SELF_REFRESH	The SDRAMC issues a Self-refresh command to the SDRAM device, the SDCK clock is deactivated and the SDCKE signal is set low. The SDRAM device leaves the Self-refresh mode when accessed and enters it after the access.
2	POWER_DOWN	The SDRAMC issues a Powerdown Command to the SDRAM device after each access, the SDCKE signal is set to low. The SDRAM device leaves the Powerdown mode when accessed and enters it after the access.
3	DEEP_POWER_DOWN	The SDRAMC issues a Deep Powerdown command to the SDRAM device. This mode is unique to low-power SDRAM.

Name:	SDRAMC_LPR
Offset:	0x10
Reset:	0x00000000
Property:	Read/Write