33.7.7 SDRAMC Interrupt Mask Register
| Name: | SDRAMC_IMR |
| Offset: | 0x1C |
| Reset: | 0x00000000 |
| Property: | Read-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| SECE | RES | ||||||||
| Access | W | R | |||||||
| Reset | 0 | 0 |
Bit 1 – SECE Security and/or Safety Event Interrupt Mask
| Value | Description |
|---|---|
| 0 |
The security and/or safety event interrupt is disabled. |
| 1 |
The security and/or safety event interrupt is enabled. |
Bit 0 – RES Refresh Error Interrupt Mask
| Value | Description |
|---|---|
| 0 | The refresh error interrupt is disabled. |
| 1 | The refresh error interrupt is enabled. |