57.7.13 ADC Last Channel Trigger Mode Register
This register can only be written if the WPEN bit is cleared in the ADC Write Protection Mode Register.
| Name: | ADC_LCTMR |
| Offset: | 0x34 |
| Reset: | 0x00000000 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CMPMOD[1:0] | DUALTRIG | ||||||||
| Access | R/W | R/W | R/W | ||||||
| Reset | 0 | 0 | 0 | ||||||
Bits 5:4 – CMPMOD[1:0] Last Channel Comparison Mode
| Value | Name | Description |
|---|---|---|
| 0 | LOW | Generates the ADC_ISR.LCCHG flag when the converted data is lower than the low threshold of the window. |
| 1 | HIGH | Generates the ADC_ISR.LCCHG flag when the converted data is higher than the high threshold of the window. |
| 2 | IN | Generates the ADC_ISR.LCCHG flag when the converted data is in the comparison window. |
| 3 | OUT | Generates the ADC_ISR.LCCHG flag when the converted data is out of the comparison window. |
Bit 0 – DUALTRIG Dual Trigger On
| Value | Description |
|---|---|
| 0 | All channels are triggered by event defined by ADC_MR.TRGSEL. |
| 1 | Last channel (higher index) trigger period is defined by RTC_MR.OUT1. |