57.7.3 ADC Channel Sequence 1 Register

This register can only be written if the WPEN bit is cleared in the ADC Write Protection Mode Register.

Name:	ADC_SEQR1
Offset:	0x08
Reset:	0x00000000
Property:	Read/Write


Bit	31	30	29	28	27	26	25	24
	USCH8[3:0]				USCH7[3:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	23	22	21	20	19	18	17	16
	USCH6[3:0]				USCH5[3:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	15	14	13	12	11	10	9	8
	USCH4[3:0]				USCH3[3:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	USCH2[3:0]				USCH1[3:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bits 0:3, 4:7, 8:11, 12:15, 16:19, 20:23, 24:27, 28:31 – USCHx User Sequence Number x

This register can be used only if the ADC_MR.USEQ field is set to ‘1’.

Any USCHx field is processed only if the ADC_CHSR.CHx-1 bit reads logical ‘1’, else any value written in USCHx does not add the corresponding channel in the conversion sequence.

Configuring the same value in different fields leads to multiple samples of the same channel during the conversion sequence. This can be done consecutively, or not, according to user needs.

Example: for each trigger event, to obtain the “CH3 CH1 CH0 CH4 CH4” conversion sequence, use the following settings:

ADC_SEQR1.USCH1=3, ADC_CHSR.CH0=1

ADC_SEQR1.USCH2=1, ADC_CHSR.CH1=1

ADC_SEQR1.USCH3=0, ADC_CHSR.CH2=1

ADC_SEQR1.USCH4=4, ADC_CHSR.CH3=1

ADC_SEQR1.USCH5=4, ADC_CHSR.CH4=1