57.7.7 ADC Channel Status Register
| Name: | ADC_CHSR |
| Offset: | 0x18 |
| Reset: | 0x00000000 |
| Property: | Read-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| CH11 | CH10 | CH9 | CH8 | ||||||
| Access | W | W | W | W | |||||
| Reset | 0 | 0 | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CH7 | CH6 | CH5 | CH4 | CH3 | CH2 | CH1 | CH0 | ||
| Access | W | W | W | W | W | W | W | W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11 – CHx Channel x Status
| Value | Description |
|---|---|
| 0 | The corresponding channel (or part of sequence, see ADC_SEQyR.USCHx field) is disabled. |
| 1 | The corresponding channel (or part of sequence, see ADC_SEQyR.USCHx field) is enabled. As an example, when ADC_MR.USEQ=1 and ADC_CHSR.CH2=1, the channel configured in ADC_SEQ1R.USCH3 is part of the sequence of conversions. |