57.7.21 ADC Pseudo-Differential Register
This register can only be written if the WPEN bit is cleared in the ADC Write Protection Mode Register.
| Name: | ADC_PDR |
| Offset: | 0xA0 |
| Reset: | 0x00000000 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| PDIFF11 | PDIFF10 | PDIFF9 | PDIFF8 | ||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| PDIFF7 | PDIFF6 | PDIFF5 | PDIFF4 | PDIFF3 | PDIFF2 | PDIFF1 | PDIFF0 | ||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11 – PDIFFx Pseudo-Differential Inputs for Channel x
| Value | Description |
|---|---|
| 0 | The channel is configured as defined by the ADC_CCR.DIFFx bit. |
| 1 | The channel is configured in Pseudo-Differential mode. |