58.7.10 PLL Characteristics

Table 58-50. PLLA Characteristics
Symbol	Parameter	Conditions	Min	Typ	Max	Unit
V_DDIN33	Supply voltage range (VDDIN33)⁽¹⁾	–	3.0	–	3.6	V
V_DDCORE	Supply voltage range (VDDCORE)	–	1.02	–	1.21	V
I_VDDIN33	Current consumption (VDDIN33)⁽²⁾	f_COREPLLCK = 1.2 GHz	–	–	3.0	mA
I_VDDCORE	Current consumption (VDDCORE)⁽²⁾	f_COREPLLCK = 1.2 GHz	–	–	3.5	mA
t_START	Startup time⁽²⁾	–	–	–	50	μs
f_IN	Input frequency range	⁽³⁾	12	–	48	MHz
f_PLLACK	Output frequency range (PLLACK)	–	–	–	600	MHz
f_COREPLLCK	COREPLLCK frequency range	–	600	–	1200	MHz

Note:

This PLL is powered by the 2.5V regulated output of the VDDOUT25 regulator, which is supplied from VDDIN33.
Simulation data
For optimal setting of the PLLA, set the register PMC_PLL_ACR to the value 0x00020010.

Table 58-51. UPLL Characteristics
Symbol	Parameter	Conditions	Min	Typ	Max	Unit
V_DDIN33	Supply voltage range (VDDIN33)⁽¹⁾	–	3.0	–	3.6	V
V_DDCORE	Supply voltage range (VDDCORE)	–	1.02	–	1.21	V
I_VDDIN33	Current consumption (VDDIN33)⁽⁵⁾	f_COREPLLCK = 960 MHz	–	–	2.4	mA
I_VDDCORE	Current consumption (VDDCORE)⁽⁵⁾	f_COREPLLCK = 960 MHz	–	–	2.8	mA
t_START	Startup time⁽³⁾⁽⁵⁾	–	–	–	150	μs
f_IN	Input frequency range⁽²⁾	⁽⁶⁾	12	–	48	MHz
f_COREPLLCK	COREPLLCK frequency range	–	600	–	1200	MHz
f_OUT	Output frequency range⁽⁴⁾	–	f_COREPLLCK / 2			MHz

Note:

This PLL is powered by an internal dedicated voltage regulator, supplied from VDDIN33, that must be started by software before enabling this PLL. Refer to Clock Generator.
Only 12, 16, 24 or 48 MHz input frequencies are authorized to support USB-related features of the bootloader program in ROM.
Covers the startup time of the PLL and of its dedicated voltage regulator.
The post divider is hardwired in a divide-by-2 configuration.
Simulation data
For optimal setting of the PLLUTMI, set the PMC_PLL_ACR as follows:
PMC_PLL_ACR = 0x09023010 for f_IN = [12 MHz, 18 MHz[
PMC_PLL_ACR = 0x12023010 for f_IN = [18 MHz, 32 MHz[
PMC_PLL_ACR = 0x1B023010 for f_IN = [32 MHz, 48 MHz]