58.7.11 12-bit ADC Characteristics

Table 58-52. ADC Power Supply and Voltage Reference Input Characteristics
Symbol	Parameter	Conditions	Min	Typ	Max	Unit
V_DDANA	Supply voltage range (VDDANA)	–	3.0	–	3.6	V
I_VDDANA	Current consumption on VDDANA⁽²⁾	Low Speed – f_S ≤ 500 kS/s ADC_ACR.IBCTL = (00)₂	–	0.7	1.0	mA
I_VDDANA	Current consumption on VDDANA⁽²⁾	Full Speed – f_S ≤ 1 MS/s ADC_ACR.IBCTL = (01)₂	–	1.2	1.7	mA
V_ADVREFP	ADVREFP input voltage range⁽¹⁾	–	2.4	–	V_DDANA	V
R_ADVREFP	ADVREFP input resistance to ground⁽²⁾	ADC on	7.2	–	12	kΩ
R_ADVREFP	ADVREFP input resistance to ground⁽²⁾	ADC off	1	–	–	MΩ
C_ADVREFP	Recommended decoupling capacitor on ADVREFP	–	1	–	–	μF

Note:

ADVREFN pin must be connected to the PCB ground plane.
Simulation data

Table 58-53. ADC Timing Characteristics
Symbol	Parameter	Conditions	Min	Typ	Max	Unit
f_CKADC	ADC clock frequency	ADC_ACR.IBCTL = (00)₂	0.1	–	10	MHz
f_CKADC	ADC clock frequency	ADC_ACR.IBCTL = (01)₂	0.2	–	20	MHz
t_CONV	ADC conversion time⁽¹⁾	–	20	–	–	t_CKADC
f_S	Sampling rate⁽²⁾	ADC_ACR.IBCTL = (00)₂	–	–	0.5	MS/s
f_S	Sampling rate⁽²⁾	ADC_ACR.IBCTL = (01)₂	–	–	1	MS/s
t_START	Startup time⁽⁴⁾	Off to on	–	–	5	μs
t_TRACK	Track and hold time⁽³⁾	–	300	–	–	ns

Note:

t_CONV= t_CH + t_TRACK + 14 x t_CKADC with t_CKADC= 1 / f_CKADC. t_CH = 0 when the ADC operates in the same input mode (single-ended, pseudo-differential or differential) for the current conversion than for the previous one. t_CH = 2 when the ADC input mode is changed to perform the current conversion.
f_S = 1 / t_CONV.
See Track and Hold Time versus Source Impedance – Sampling Rate.
Simulation data

Table 58-54. ADC Analog Input Characteristics
Symbol	Parameter	Conditions	Min	Typ	Max	Unit
V_FS	Analog input full scale range⁽¹⁾	ADC_CCR.DIFFx = 0	0	–	V_ADVREF	V
V_FS	Analog input full scale range⁽¹⁾	ADC_CCR.DIFFx = 1	-V_ADVREF	–	V_ADVREF	V
V_INCM	Common mode input range in Differential Input mode⁽²⁾	ADC_CCR.DIFFx = 1	0.4 x V_DDANA	–	0.6 x V_DDANA	V
C_S	ADC sampling capacitance⁽⁵⁾	–	–	–	3	pF
C_{P_ADx}	ADx input parasitic capacitance⁽³⁾⁽⁵⁾	ADx pin configured as analog input	–	–	7	pF
R_ON	Internal series resistor⁽³⁾⁽⁵⁾	–	–	–	2	kΩ
Z_IN	Common mode input impedance⁽⁴⁾⁽⁵⁾	On ADx pin	1 / (f_S.C_S)	–	–	Ω

Note:

V_FS = (V_ADx- V_GNDANA) in Single-ended mode, V_FS = (V_ADx- V_AD11) in Pseudo-differential mode, and V_FS= (V_ADx- V_ADx+1) in Differential mode.
V_INCM= (V_ADx + V_ADx+1) / 2.
With respect to the equivalent model of figure Equivalent Model of the Acquisition Path.
Assuming conversion on one single channel
Simulation data

Figure 58-37. Acquisition Path Block Diagram

For tracking time calculation, during the sampling phase of the converter, this acquisition path can be reduced to the equivalent model provided in the following figure, where:

R_ON = R_MUX + R_S
C_{P_ADX} = C_PX + C_{P_MUX}

Figure 58-38. Equivalent Model of the Acquisition Path

See Track and Hold Time versus Source Impedance – Sampling Rate for further details on how to use this model.

In the following table, unless otherwise specified, the specifications are given for two speed operating ranges.

Source resistance = 50 Ω
ADC_EMR.OSR<2:0> = (000)₂
Low-speed
- f_CKADC = 10 MHz, f_S = 500 kS/s
- ADC_ACR.IBCTL = (00)₂
High-speed
- f_CKADC = 20 MHz, f_S = 1 MS/s
- ADC_ACR.IBCTL = (01)₂

Table 58-55. Static Performance Characteristics⁽¹⁾
Symbol	Parameter	Conditions	Min	Typ	Max	Unit
RES_ADC	Native ADC resolution	–	–	12	–	Bit
INL	Integral non-linearity	Single mode	-3	–	+3	LSB
INL	Integral non-linearity	Differential mode⁽³⁾	-2	–	+2	LSB
DNL	Differential non-linearity	Single mode	-2	–	+2	LSB
DNL	Differential non-linearity	Differential mode⁽³⁾	-1		+1	LSB
OE	Offset error⁽²⁾	–	-4	–	4	LSB
GE	Gain error⁽²⁾	–	-4	–	4	LSB

Warning: ADC channels should be selected knowing that toggling the QSPI I/Os may decrease ADC channel 4 and 0 performances.

Note: