15.6.11 Peripheral Write Protection Status C

Reading the STATUSC register returns the peripheral write protection status:

ValueDescription
0Peripheral is not write protected.
1Peripheral is write protected.
Important: For PIC32CM LS00/LS60 Non-Secure accesses, read accesses (R*) are allowed only if the peripheral security attribution for the corresponding peripheral is set as Non-Secured in the NONSECx register.
Name: STATUSC
Offset: 0x3C
Reset: 0x000000
Property: Mix-Secure

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
   TRAMOPAMPI2SCCLTRNGPTC 
Access R/R*/RR/R*/RR/R*/RR/R*/RR/R*/RR/R*/R 
Reset 000000 
Bit 15141312111098 
 DACADCTCC3TCC2TCC1TCC0TC2TC1 
Access R/R*/RR/R*/RR/R*/RR/R*/RR/R*/RR/R*/RR/R*/RR/R*/R 
Reset 00000000 
Bit 76543210 
 TC0SERCOM5SERCOM4SERCOM3SERCOM2SERCOM1SERCOM0EVSYS 
Access R/R*/RR/R*/RR/R*/RR/R*/RR/R*/RR/R*/RR/R*/RR/R*/R 
Reset 00000000 

Bit 21 – TRAM Peripheral TRAM Write Protection Status

Bit 20 – OPAMP Peripheral OPAMP Write Protection Status

Bit 19 – I2S Peripheral I2S Write Protection Status

Bit 18 – CCL Peripheral CCL Write Protection Status

Bit 17 – TRNG Peripheral TRNG Write Protection Status

Bit 16 – PTC Peripheral PTC Write Protection Status

Bit 15 – DAC Peripheral DAC Write Protection Status

Bit 14 – ADC Peripheral ADC Write Protection Status

Bits 10, 11, 12, 13 – TCC Peripheral TCn Write Protection Status [n = 3..0]

Bits 7, 8, 9 – TC Peripheral TCn Write Protection Status [n = 2..0]

Bits 1, 2, 3, 4, 5, 6 – SERCOM Peripheral SERCOMn Write Protection Status [n = 5..0]

Bit 0 – EVSYS Peripheral EVSYS Write Protection Status