5.7.6.45 CSI2DC Data Pipe Interrupt Clear Register
| Name: | CSI2DC_DPICR |
| Offset: | 0xD8 |
| Reset: | – |
| Property: | Write-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| LTE | STE | DATOVF | RXOVF1 | RXOVF0 | RXRDY1 | RXRDY0 | CAPTURE | ||
| Access | W | W | W | W | W | W | W | W | |
| Reset | – | – | – | – | – | – | – | – |
Bit 7 – LTE Packet Longer Than Expected Interrupt Clear Register
| Value | Description |
|---|---|
| 0 | No effect. |
| 1 | Clears the LTE interrupt. |
Bit 6 – STE Packet Shorter Than Expected Interrupt Clear Register
| Value | Description |
|---|---|
| 0 | No effect. |
| 1 | Clears the STE interrupt. |
Bit 5 – DATOVF Data Overflow Interrupt Clear Register
| Value | Description |
|---|---|
| 0 | No effect. |
| 1 | Clears the Data Overflow interrupt. |
Bit 4 – RXOVF1 Bank 1 Packet Overflow Interrupt Clear Register
| Value | Description |
|---|---|
| 0 | No effect. |
| 1 | Clears the Bank 1 Packet Overflow interrupt. |
Bit 3 – RXOVF0 Bank 0 Packet Overflow Interrupt Clear Register
| Value | Description |
|---|---|
| 0 | No effect. |
| 1 | Clears the Bank 0 Packet Overflow interrupt. |
Bit 2 – RXRDY1 Bank 1 Packet Received Interrupt Clear Register
| Value | Description |
|---|---|
| 0 | No effect. |
| 1 | Clears the Bank 1 Packet Received interrupt. |
Bit 1 – RXRDY0 Bank 0 Packet Received Interrupt Clear Register
| Value | Description |
|---|---|
| 0 | No effect. |
| 1 | Clears the Bank 0 Packet Received interrupt. |
Bit 0 – CAPTURE Captured Frame Interrupt Clear Register
| Value | Description |
|---|---|
| 0 | No effect. |
| 1 | Clears the Captured Frame interrupt. |