11.1.2 Cortex-M23 Core Peripherals

The processor has the following core peripheral:
  • System Timer (SysTick)
    • The System Timer is a 24-bit timer clocked by the core frequency.
      Important: On SAM L11 devices, there are two System timers, one for Secure state and one for Non-Secure state.
  • Nested Vectored Interrupt Controller (NVIC)
    • The NVIC is an embedded interrupt controller that supports low latency interrupt processing.
      Important: On SAM L11 devices, there are two Vector tables: the Secure Vector table and the Non-Secure Vector table.
  • System Control Block (SCB)
    • The System Control Block (SCB) provides system implementation information and system control that includes configuration, control, and reporting of system exceptions
  • Memory Protection Unit (MPU)
    • The MPU improves system reliability by defining the memory attributes for different memory regions.
      Important: On SAM L11 devices, there are two MPUs: one for the Secure state and one for the Non-Secure state. Each MPU can define memory access permissions and attributes independently.
  • Security Attribution Unit (SAU)
    • The SAU improves system security by defining security attributes for different regions.
      Important: The SAU is absent from SAM L10 and SAM L11 devices.

For more details, refer to the ARM Cortex-M23 Processor Technical Reference Manual (www.arm.com).

Table 11-2. Cortex-M23 Core Peripherals Address Map
Core Peripherals

Base Address

(SAM L10 and SAM L11)

(Non-Secure) Alias Base Address

(SAM L11 only)
System Timer (SysTick) 0xE000E010 0xE002E010
Nested Vectored Interrupt Controller (NVIC) 0xE000E100 0xE002E100
System Control Block (SCB) 0xE000ED00 0xE002ED00
Memory Protection Unit (MPU) 0xE000ED90 0xE002ED90