22.6.3.3 Sleep Mode Controller

Sleep mode is entered by executing the Wait For Interrupt instruction (WFI). The Sleep Mode bits in the Sleep Configuration register (SLEEPCFG.SLEEPMODE) select the level of the sleep mode.

Note: A small latency happens between the store instruction and actual writing of the SLEEPCFG register due to bridges. Software must ensure that the SLEEPCFG register reads the desired value before issuing a WFI instruction.
Note: After power-up, the MAINVREG low power mode takes some time to stabilize. Once stabilized, the SUPC->STATUS.ULPVREFRDY bit is set. Before entering Standby, software must ensure that the SUPC->STATUS.ULPVREFRDY bit is set.
Table 22-1. Sleep Mode Entry and Exit Table
Mode Mode Entry Wake-Up Sources
IDLE SLEEPCFG.SLEEPMODE = IDLE
_n Synchronous (2) (APB, AHB), asynchronous (1)
STANDBY SLEEPCFG.SLEEPMODE = STANDBY
 Synchronous(3), Asynchronous
OFF SLEEPCFG.SLEEPMODE = OFF
 External Reset
Note:
  1. Asynchronous: interrupt generated on generic clock, external clock, or external event.
  2. Synchronous: interrupt generated on the APB clock.
  3. Synchronous interrupt only for peripherals configured to run in standby.
Note: The type of wake-up sources (synchronous or asynchronous) is given in each module interrupt section.

The sleep modes (idle, standby, and off) and their effect on the clocks activity, the regulator and the NVM state are described in the table and the sections below. Refer to Power Domain Controller for the power domain gating effect.

Table 22-2. Sleep Mode Overview
Mode Main clock CPU AHBx and APBx clock GCLK clocks Oscillators Regulator NVM
ONDEMAND = 0 ONDEMAND = 1
Active Run Run Run Run(3) Run Run if requested MAINVREG active
IDLE Run Stop Stop(1) Run(3) Run Run if requested MAINVREG active
STANDBY Stop(1) Stop Stop(1) Stop(1) Run if requested or RUNSTDBY=1 Run if requested MAINVREG in low power mode Ultra Low- power
OFF Stop Stop Stop OFF OFF OFF OFF OFF
Note:
  1. Running if requested by peripheral during SleepWalking.
  2. Running during SleepWalking.
  3. Following On-Demand Clock Request principle.