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22.7 Register Summary
| Offset | Name | Bit Pos. | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|
0x00 | Reserved | | | | | | | | | |
| 0x01 | SLEEPCFG | 7:0 | | | | | | SLEEPMODE[2:0] |
| 0x02 | PLCFG | 7:0 | PLDIS | | | | | | PLSEL[1:0] |
| 0x03 | PWCFG | 7:0 | | | | | | | RAMPSWC[1:0] |
| 0x04 | INTENCLR | 7:0 | | | | | | | | PLRDY |
| 0x05 | INTENSET | 7:0 | | | | | | | | PLRDY |
| 0x06 | INTFLAG | 7:0 | | | | | | | | PLRDY |
0x07 | Reserved | | | | | | | | | |
| 0x08 | STDBYCFG | 7:0 | VREGSMOD[1:0] | | DPGPDSW | | | | PDCFG |
| 15:8 | | | | BBIASTR | | BBIASHS | | |
