19.6.2.6 Peripheral Clock Masking

The user can disable or enable the AHB or APB clock for a peripheral by writing the corresponding bit in the Clock Mask registers (APBxMASK) to '0' or '1'. The default state of the peripheral clocks is provided in the table below.

Table 19-1. Peripheral Clock Default State
CPU Clock Domain
Peripheral Clock Default State
CLK_AC_APB Enabled
CLK_ADC_APB Enabled
CLK_APBA_AHB Enabled
CLK_APBB_AHB Enabled
CLK_APBC_AHB Enabled
CLK_CCL_APB Enabled
CLK_DAC_APB Enabled
CLK_DMAC_AHB Enabled
CLK_DSU_AHB Enabled
CLK_DSU_APB Enabled
CLK_EIC_APB Enabled
CLK_EVSYS_APB Enabled
CLK_FREQM_APB Enabled
CLK_GCLK_APB Enabled
CLK_HMATRIXHS_APB Enabled
CLK_MCLK_APB Enabled
CLK_NVMCTRL_AHB Enabled
CLK_NVMCTRL_APB Enabled
CLK_OPAMP_APB Enabled
CLK_OSCCTRL_APB Enabled
CLK_OSC32CTRL_APB Enabled
CLK_PAC_AHB Enabled
CLK_PAC_APB Enabled
CLK_PORT_APB Enabled
CLK_PM_APB Enabled
CLK_PTC_APB Enabled
CLK_RSTC_APB Enabled
CLK_RTC_APB Enabled
CLK_SERCOM0_APB Enabled
CLK_SERCOM1_APB Enabled
CLK_SERCOM2_APB(1) Enabled
CLK_SUPC_APB Enabled
CLK_TC0_APB Enabled
CLK_TC1_APB Enabled
CLK_TC2_APB Enabled
CLK_TRAM_AHB Enabled
CLK_TRNG_APB Enabled
CLK_WDT_APB Enabled
Note: 1. SERCOM2 Peripheral Clock is disabled for all 24-pin packages as SERCOM2 is not present.

When the APB clock is not provided to a module, its registers cannot be read or written. The module can be re-enabled later by writing the corresponding mask bit to '1'.

A module may be connected to several clock domains (for instance, AHB and APB), in which case it will have several mask bits.

The clocks must be switched off if it is certain that the module will not be used: Switching off the clock for the NVM Controller (NVMCTRL) will cause a problem if the CPU needs to read from the Flash memory. Switching off the clock to the MCLK module (which contains the mask registers) or the corresponding APBx bridge will make it impossible to write the mask registers again. In this case, they can only be re-enabled by a system reset.