19.6.2.6 Peripheral Clock Masking

The user can disable or enable the AHB or APB clock for a peripheral by writing the corresponding bit in the Clock Mask registers (APBxMASK) to '0' or '1'. The default state of the peripheral clocks is provided in the table below.

Table 19-1. Peripheral Clock Default State
CPU Clock Domain
Peripheral ClockDefault State
CLK_AC_APBEnabled
CLK_ADC_APBEnabled
CLK_APBA_AHBEnabled
CLK_APBB_AHBEnabled
CLK_APBC_AHBEnabled
CLK_CCL_APBEnabled
CLK_DAC_APBEnabled
CLK_DMAC_AHBEnabled
CLK_DSU_AHBEnabled
CLK_DSU_APBEnabled
CLK_EIC_APBEnabled
CLK_EVSYS_APBEnabled
CLK_FREQM_APBEnabled
CLK_GCLK_APBEnabled
CLK_HMATRIXHS_APBEnabled
CLK_MCLK_APBEnabled
CLK_NVMCTRL_AHBEnabled
CLK_NVMCTRL_APBEnabled
CLK_OPAMP_APBEnabled
CLK_OSCCTRL_APBEnabled
CLK_OSC32CTRL_APBEnabled
CLK_PAC_AHBEnabled
CLK_PAC_APBEnabled
CLK_PORT_APBEnabled
CLK_PM_APBEnabled
CLK_PTC_APBEnabled
CLK_RSTC_APBEnabled
CLK_RTC_APBEnabled
CLK_SERCOM0_APBEnabled
CLK_SERCOM1_APBEnabled
CLK_SERCOM2_APB(1)Enabled
CLK_SUPC_APBEnabled
CLK_TC0_APBEnabled
CLK_TC1_APBEnabled
CLK_TC2_APBEnabled
CLK_TRAM_AHBEnabled
CLK_TRNG_APBEnabled
CLK_WDT_APBEnabled
Note: 1. SERCOM2 Peripheral Clock is disabled for all 24-pin packages as SERCOM2 is not present.

When the APB clock is not provided to a module, its registers cannot be read or written. The module can be re-enabled later by writing the corresponding mask bit to '1'.

A module may be connected to several clock domains (for instance, AHB and APB), in which case it will have several mask bits.

The clocks must be switched off if it is certain that the module will not be used: Switching off the clock for the NVM Controller (NVMCTRL) will cause a problem if the CPU needs to read from the Flash memory. Switching off the clock to the MCLK module (which contains the mask registers) or the corresponding APBx bridge will make it impossible to write the mask registers again. In this case, they can only be re-enabled by a system reset.