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Ultra Low-Power, 32-bit Cortex-M23 MCUs with TrustZone, Crypto, and Enhanced PTC
Ultra Low-Power, 32-bit Cortex-M23 MCUs with TrustZone, Crypto, and Enhanced PTC
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ATSAML10D14A ATSAML10D15A ATSAML10D16A ATSAML10E14A ATSAML10E15A ATSAML10E16A ATSAML11D14A ATSAML11D15A ATSAML11D16A ATSAML11E14A ATSAML11E15A ATSAML11E16A
  1. Home
  2. 37 SERCOM I2C – SERCOM Inter-Integrated Circuit
  3. 37.6 Functional Description
  4. 37.6.2 Basic Operation
  5. 37.6.2.4 I2C Host Operation
  6. 37.6.2.4.1 Host Clock Generation
  • Features
  • 1 Configuration Summary
  • 2 Ordering Information
  • 3 Block Diagram
  • 4 Pinouts
  • 5 Signal Descriptions List
  • 6 Power Considerations
  • 7 Analog Peripherals Considerations
  • 8 Device Startup
  • 9 Product Mapping
  • 10 Memories
  • 11 Processor and Architecture
  • 12 Peripherals Configuration Summary
  • 13 SAM L11 Specific Security Features
  • 14 Boot ROM
  • 15 PAC - Peripheral Access Controller
  • 16 Device Service Unit (DSU)
  • 17 Clock System
  • 18 GCLK - Generic Clock Controller

  • 19 MCLK – Main Clock
  • 20 FREQM – Frequency Meter
  • 21 RSTC – Reset Controller
  • 22 PM – Power Manager
  • 23 OSCCTRL – Oscillators Controller
  • 24 OSC32KCTRL – 32KHz Oscillators Controller
  • 25 SUPC – Supply Controller
  • 26 WDT – Watchdog Timer
  • 27 RTC – Real-Time Counter
  • 28 DMAC – Direct Memory Access Controller
  • 29 EIC – External Interrupt Controller
  • 30 NVMCTRL – Nonvolatile Memory Controller
  • 31 TrustRAM (TRAM)
  • 32 PORT - I/O Pin Controller
  • 33 EVSYS – Event System
  • 34 SERCOM – Serial Communication Interface
  • 35 SERCOM USART - SERCOM Synchronous and Asynchronous Receiver and Transmitter
  • 36 SERCOM SPI – SERCOM Serial Peripheral Interface
  • 37 SERCOM I2C – SERCOM Inter-Integrated Circuit
    • 37.1 Overview
    • 37.2 Features
    • 37.3 Block Diagram
    • 37.4 Signal Description
    • 37.5 Product Dependencies
    • 37.6 Functional Description
      • 37.6.1 Principle of Operation
      • 37.6.2 Basic Operation
        • 37.6.2.1 Initialization
        • 37.6.2.2 Enabling, Disabling, and Resetting
        • 37.6.2.3 I2C Bus State Logic
        • 37.6.2.4 I2C Host Operation
          • 37.6.2.4.1 Host Clock Generation
            • 37.6.2.4.1.1 Clock Generation (Standard-Mode, Fast-Mode, and Fast-Mode Plus)
            • 37.6.2.4.1.2 Host Clock Generation (High-Speed Mode)
          • 37.6.2.4.2 Transmitting Address Packets
          • 37.6.2.4.3 Transmitting Data Packets
          • 37.6.2.4.4 Receiving Data Packets (SCLSM=0)
          • 37.6.2.4.5 Receiving Data Packets (SCLSM=1)
          • 37.6.2.4.6 High-Speed Mode
          • 37.6.2.4.7 10-Bit Addressing
        • 37.6.2.5 I2C Client Operation
      • 37.6.3 Additional Features
      • 37.6.4 DMA, Interrupts and Events
      • 37.6.5 Sleep Mode Operation
      • 37.6.6 Synchronization
    • 37.7 Register Summary - I2C Client
    • 37.8 Register Description - I2C Client
    • 37.9 Register Summary - I2C Host
    • 37.10 Register Description - I2C Host
  • 38 TC – Timer/Counter
  • 39 TRNG – True Random Number Generator
  • 40 CCL – Configurable Custom Logic
  • 41 ADC – Analog-to-Digital Converter
  • 42 AC – Analog Comparators
  • 43 DAC – Digital-to-Analog Converter
  • 44 OPAMP – Operational Amplifier Controller
  • 45 PTC - Peripheral Touch Controller
  • 46 Electrical Characteristics
  • 47 125°C Electrical Characteristics
  • 48 AEC-Q100 Grade (-40°C to 125°C) Electrical Characteristics
  • 49 AC and DC Characteristics Graphs
  • 50 Packaging Information
  • 51 Schematic Checklist
  • 52 Conventions
  • 53 Acronyms and Abbreviations
  • 54 Appendix A: Migrating From SAM L21 to SAM L10/L11 (32-pin Package)
  • 55 Appendix B: Migrating From SAM D20/D21 to SAM L10/L11 (32-pin Package)
  • 56 Revision History
  • Legal Disclaimer
  • Microchip Information

37.6.2.4.1 Host Clock Generation

The SERCOM peripheral supports several I2C bidirectional modes:
  • Standard mode (Sm) up to 100 kHz
  • Fast mode (Fm) up to 400 kHz
  • Fast mode Plus (Fm+) up to 1 MHz
  • High-speed mode (Hs) up to 3.4 MHz
The Host clock configuration for Sm, Fm, and Fm+ are described in 37.6.2.4.1.1 Clock Generation (Standard-Mode, Fast-Mode, and Fast-Mode Plus). For Hs, refer to 37.6.2.4.1.2 Host Clock Generation (High-Speed Mode).

The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.

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