10.1.2 Data Flash
The SAM L10/L11 devices embed 2 KB of internal Data Flash with Write-While-Read (WWR) capability mapped at address 0x0040 0000.
The Data Flash can be programmed or erased while reading the Flash memory. It is
not possible to read the Data Flash while writing or erasing the Flash.
Note: The Data Flash memory can be
executable but requires more cycles to be read which may affect system
performance.
The Data Flash cannot be cached. The Data Flash is organized into rows, where each row contains four pages. The Data Flash has a row-erase and a page-write granularity.
CAUTION: For this Flash technology, a maximum number of 8 consecutive writes is
allowed per row. Once this number is reached, a row erase is mandatory.
| Device | Memory Size [KB] | Number of Rows | Row size [Bytes] | Number of Pages | Page size [Bytes] |
|---|---|---|---|---|---|
| SAM L10/L11 | 2 | 8 | 256 | 32 | 64 |
The Data Flash is divided into one or two regions. Each region has a dedicated lock bit preventing from writing and erasing pages on it. Refer to the NVM Memory Organization figures in the Chapter “NVMCTR” to obtain the definitions of the different regions.
Note: The regions size is configured by the Boot
ROM at device startup by reading the NVM Boot Configuration Row (BOCOR).
| Device | SAM L10 | SAM L11 |
|---|---|---|
| Number of Data FLASH Lock Regions | 1 | 2 |
| Regions Name | Data Flash | Secure Data Flash / Non-Secure Data Flash |