11.2.2 Interrupt Line Mapping

Each interrupt line is connected to one peripheral instance, as shown in the table below. Each peripheral can have one or more interrupt flags, located in the peripheral’s Interrupt Flag Status and Clear (INTFLAG) register.

An interrupt flag is set when the interrupt condition occurs. Each interrupt in the peripheral can be individually enabled by writing a 1 to the corresponding bit in the peripheral’s Interrupt Enable Set (INTENSET) register, and disabled by writing 1 to the corresponding bit in the peripheral’s Interrupt Enable Clear (INTENCLR) register.

An interrupt request is generated from the peripheral when the interrupt flag is set and the corresponding interrupt is enabled.

The interrupt requests for one peripheral are ORed together on system level, generating one interrupt request for each peripheral. An interrupt request will set the corresponding interrupt pending bit in the NVIC interrupt pending registers (SETPEND/CLRPEND bits in ISPR/ICPR).

For the NVIC to activate the interrupt, it must be enabled in the NVIC interrupt enable register (SETENA/CLRENA bits in ISER/ICER). The NVIC interrupt priority registers IPR0-IPR11 provide a priority field for each interrupt.

Table 11-3. Interrupt Line Mapping
Module Source NVIC line
EIC NMI – External Interrupt Controller NMI NMI

PM – Power Manager

PLRDY 0
MCLK - Main Clock CKRDY
OSCCTRL - Oscillators Controller XOSCRDY
CLKFAIL
OSC16MRDY
DFLLULPRDY
DFLLULPLOCK
DFLLULPNOLOCK
DPLLLCKR
DPLLLCKF
DPLLLTO
DPLLLDRTO
OSC32KCTRL - 32KHz Oscillators Controller XOSC32KRDY
CLKFAIL
SUPC - Supply Controller BOD33RDY
BOD33DET
B33SRDY
VREGRDY
VCORERDY
ULPVREFRDY
WDT – Watchdog Timer EW 1
RTC – Real Time Counter CMP0 2
CMP1
OVF
PER0
PER1
PER2
PER3
PER4
PER5
PER6
PER7
TAMPER
EIC – External Interrupt Controller EXTINT 0 3
EXTINT 1 4
EXTINT 2 5
EXTINT 3 6
EXTINT 4..7 7
NSCHK(1)
FREQM - Frequency Meter DONE 8
NVMCTRL – Non-Volatile Memory Controller DONE 9
PROGE
LOCKE
NVME
KEYE
NSCHK(1)
PORT - I/O Pin Controller NSCHK(1) 10
DMAC - Direct Memory Access Controller SUSP 0 11
TERR 0
TCMPL 0
SUSP 1 12
TERR 1
TCMPL 1
SUSP 2 13
TERR 2
TCMPL 2
SUSP 3 14
TERR 3
TCMPL 3
SUSP 4..7 15
TERR 4..7
TCMPL 4..7
EVSYS – Event System EVD 0 16
OVR 0
EVD 1 17
OVR 1
EVD 2 18
OVR 2
EVD 3 19
OVR 3
NSCHK(1) 20
PAC - Peripheral Access Controller ERR 21
SERCOM0 – Serial Communication Interface 0 (Interrupt Sources vary depending on SERCOM mode) Interrupt Bit 0 22
Interrupt Bit 1 23
Interrupt Bit 2 24
Interrupt Bits 3..6 25
SERCOM1 – Serial Communication Interface 1 (Interrupt Sources vary depending on SERCOM mode) Interrupt Bit 0 26
Interrupt Bit 1 27
Interrupt Bit 2 28
Interrupt Bit 3..6 29
SERCOM2 – Serial Communication Interface 2 (Interrupt Sources vary depending on SERCOM mode) Interrupt Bit 0 30
Interrupt Bit 1 31
Interrupt Bit 2 32
Interrupt Bits 3..6 33
TC0 – Timer Counter 0 ERR A 34
MC 0
MC 1
OVF
TC1 – Timer Counter 1 ERR A 35
MC 0
MC 1
OVF
TC2 – Timer Counter 2 ERR A 36
MC 0
MC 1
OVF
ADC – Analog-to-Digital Converter OVERRUN 37
WINMON
RESRDY 38
AC – Analog Comparator COMP 0 39
COMP 1
WIN 0
DAC – Digital-to-Analog Converter UNDERRUN 40
EMPTY 41
PTC – Peripheral Touch Controller EOC 42
WCOMP
TRNG - True Random Number Generator DATARDY 43
TRAM - TrustRAM DRP 44
ERR
Note:
  1. NSCHK interrupt sources will not generate any interrupts for SAM L10 devices.