27.7.6.1 Control A in Clock/Calendar mode (CTRLA.MODE=2)

Name: CTRLA
Offset: 0x00
Reset: 0x0000
Property: PAC Write-Protection, Enable-Protected Bits, Write-Synchronized Bits

Bit 15141312111098 
 CLOCKSYNCGPTRST  PRESCALER[3:0] 
Access R/WR/WR/WR/WR/WR/W 
Reset 000000 
Bit 76543210 
 MATCHCLRCLKREP  MODE[1:0]ENABLESWRST 
Access R/WR/WR/WR/WR/WR/W 
Reset 000000 

Bit 15 – CLOCKSYNC CLOCK Read Synchronization Enable

The CLOCK register requires synchronization when reading. Disabling the synchronization will prevent reading valid values from the CLOCK register.

This bit is not enable-protected.

ValueDescription
0 CLOCK read synchronization is disabled
1 CLOCK read synchronization is enabled

Bit 14 – GPTRST GP Registers Reset On Tamper Enable

Only GP registers enabled by the CTRLB.GPnEN bits are affected. This bit can be written only when the peripheral is disabled.

This bit is not synchronized.

Bits 11:8 – PRESCALER[3:0] Prescaler

These bits define the prescaling factor for the RTC clock source (GCLK_RTC) to generate the counter clock (CLK_RTC_CNT). Periodic events and interrupts are not available when the prescaler is off. These bits are not synchronized.
ValueNameDescription
0x0 OFF CLK_RTC_CNT = GCLK_RTC/1
0x1 DIV1 CLK_RTC_CNT = GCLK_RTC/1
0x2 DIV2 CLK_RTC_CNT = GCLK_RTC/2
0x3 DIV4 CLK_RTC_CNT = GCLK_RTC/4
0x4 DIV8 CLK_RTC_CNT = GCLK_RTC/8
0x5 DIV16 CLK_RTC_CNT = GCLK_RTC/16
0x6 DIV32 CLK_RTC_CNT = GCLK_RTC/32
0x7 DIV64 CLK_RTC_CNT = GCLK_RTC/64
0x8 DIV128 CLK_RTC_CNT = GCLK_RTC/128
0x9 DIV256 CLK_RTC_CNT = GCLK_RTC/256
0xA DIV512 CLK_RTC_CNT = GCLK_RTC/512
0xB DIV1024 CLK_RTC_CNT = GCLK_RTC/1024
0xC-0xF - Reserved

Bit 7 – MATCHCLR Clear on Match

This bit is valid only in Mode 0 (COUNT32) and Mode 2 (CLOCK). This bit can be written only when the peripheral is disabled. This bit is not synchronized.
ValueDescription
0 The counter is not cleared on a Compare/Alarm 0 match
1 The counter is cleared on a Compare/Alarm 0 match

Bit 6 – CLKREP Clock Representation

This bit is valid only in Mode 2 and determines how the hours are represented in the Clock Value (CLOCK) register. This bit can be written only when the peripheral is disabled. This bit is not synchronized.
ValueDescription
0 24 Hour
1 12 Hour (AM/PM)

Bits 3:2 – MODE[1:0] Operating Mode

This field defines the operating mode of the RTC. This bit is not synchronized.
ValueNameDescription
0x0 COUNT32 Mode 0: 32-bit counter
0x1 COUNT16 Mode 1: 16-bit counter
0x2 CLOCK Mode 2: Clock/calendar
0x3 - Reserved

Bit 1 – ENABLE Enable

Due to synchronization there is delay from writing CTRLA.ENABLE until the peripheral is enabled/disabled. The value written to CTRLA.ENABLE will read back immediately and the Enable bit in the Synchronization Busy register (SYNCBUSY.ENABLE) will be set. SYNCBUSY.ENABLE will be cleared when the operation is complete.

This bit is not enable-protected.

ValueDescription
0 The peripheral is disabled
1 The peripheral is enabled

Bit 0 – SWRST Software Reset

Writing a '0' to this bit has no effect.

Writing a '1' to this bit resets all registers in the RTC, except DBGCTRL, to their initial state, and the RTC will be disabled.

Writing a '1' to CTRLA.SWRST will always take precedence, meaning that all other writes in the same write-operation will be discarded.

This bit is not enable-protected.

Note:
  1. When the CTRLA.SWRST is written, the user must poll the SYNCBUSY.SWRST bit to know when the reset operation is complete.
  2. During a SWRST, access to registers/bits without SWRST are disallowed until the SYNCBUSY.SWRST is cleared by hardware.
ValueDescription
0 There is not reset operation ongoing
1 The reset operation is ongoing