37.4.8 I3CxPIR0

Note:

Will not self-clear after the event. The user must clear this bit to re-arm.
The Start/Restart/Stop flags do not operate when the bus is in HDR mode (OPMD = 1x).
This bit is valid in I²C mode only. For I3C mode, the process of Controller acknowledging bus arbitration request is handled separately through In-Band Interrupt and Hot-Join requests.
This bit is set for all supported Broadcast CCCs and only for those supported Direct CCCs that address the Target.
In case of a race condition, user writes always take precedence over hardware events.

Name:	I3CxPIR0
Address:	0x08A, 0x0BD

General Interrupt Flag 0


Bit	7	6	5	4	3	2	1	0
	SCIF	PCIF	RSCIF	I2CACKIF	SADRIF	DADRIF	BTFIF	SCCCIF
Access	R/W/HS	R/W/HS	R/W/HS	R/W/HS	R/W/HS	R/W/HS	R/W/HS	R/W/HS
Reset	0	0	0	0	0	0	0	0

Bit 7 – SCIF Start Condition Interrupt Flag^{(1, 2)}

Value	Description
1	Start condition detected
0	Start condition not detected

Bit 6 – PCIF Stop Condition Interrupt Flag^{(1, 2)}

Value	Description
1	Stop condition detected
0	Stop condition not detected

Bit 5 – RSCIF Restart Condition Interrupt Flag^{(1, 2)}

Value	Description
1	Restart condition detected
0	Restart condition not detected

Bit 4 – I2CACKIF I²C Acknowledge (ACK) Received Interrupt Flag^{(1, 3)}

Value	Description
1	ACK received from the Controller during I²C Transmit
0	ACK not received

Bit 3 – SADRIF Static Address Match Interrupt Flag⁽¹⁾

Value	Description
1	Static Address (I3CxSADR) match detected during a Private/I²C Transaction
0	Static Address (I3CxSADR) match not detected

Bit 2 – DADRIF Dynamic Address Match Interrupt Flag⁽¹⁾

Value	Description
1	Dynamic Address (I3CxDADR) match detected during a Private Transaction
0	Dynamic Address (I3CxDADR) match not detected

Bit 1 – BTFIF Byte Transfer Finished Interrupt Flag⁽¹⁾

Value	Description
1	A byte transfer finished
0	Byte transfer not finished or not started

Bit 0 – SCCCIF Supported CCC Received Interrupt Flag^{(1, 4)}

Value	Description
1	A supported CCC was received
0	No supported CCCs were received

Will not self-clear after the event. The user must clear this bit to re-arm. The Start/Restart/Stop flags do not operate when the bus is in HDR mode (OPMD Operating Mode Status = 1x). This bit is valid in I2C mode only. For I3C mode, the process of Controller acknowledging bus arbitration request is handled separately through In-Band Interrupt and Hot-Join requests. This bit is set for all supported Broadcast CCCs and only for those supported Direct CCCs that address the Target. In case of a race condition, user writes always take precedence over hardware events.