37.4.26 I3CxMRL
Note:
- The Controller may update the value of this register by issuing a SETMRL CCC.
- In case of a race condition, user writes always take precedence over hardware events.
| Name: | I3CxMRL |
| Address: | 0x09F, 0x0D2 |
Maximum Read Length
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| MRL[15:0] | |||||||||
| Access | R/W/HS/HC | R/W/HS/HC | R/W/HS/HC | R/W/HS/HC | R/W/HS/HC | R/W/HS/HC | R/W/HS/HC | R/W/HS/HC | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| MRL[15:0] | |||||||||
| Access | R/W/HS/HC | R/W/HS/HC | R/W/HS/HC | R/W/HS/HC | R/W/HS/HC | R/W/HS/HC | R/W/HS/HC | R/W/HS/HC | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bits 15:0 – MRL[15:0] Maximum Read Length
| Value | Description |
|---|---|
| other | Maximum Read Length in bytes |
| 0 | Unlimited Maximum Read Length |