11.13.24 PIR7

Peripheral Interrupt Request Register 7

Note:

Interrupt flag bits get set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit. User software must ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.
I2C1EIF is a read-only bit. To clear the interrupt condition, all bits in the I2C1ERR register must be cleared.
I2C1IF is a read-only bit. To clear the interrupt condition, all bits in the I2C1PIR register must be cleared.
I2C1TXIF and I2C1RXIF are read-only bits. To clear the interrupt condition, the CLRBF bit in I2C1STAT1 must be set.
SPI1IF is a read-only bit. To clear the interrupt condition, all bits in the SPI1INTF register must be cleared.
SPI1TXIF and SPI1RXIF are read-only bits and cannot be set/cleared by software.

Name:	PIR7
Address:	0x470


Bit	7	6	5	4	3	2	1	0
		I2C1EIF	I2C1IF	I2C1TXIF	I2C1RXIF	SPI1IF	SPI1TXIF	SPI1RXIF
Access		R	R	R	R	R	R	R
Reset		0	0	0	0	0	0	0

Bit 6 – I2C1EIF I2C1 Error Interrupt Flag⁽²⁾

Value	Description
1	Interrupt has occurred
0	Interrupt event has not occurred

Bit 5 – I2C1IF I2C1 Interrupt Flag⁽³⁾

Value	Description
1	Interrupt has occurred
0	Interrupt event has not occurred

Bit 4 – I2C1TXIF I2C1 Transmit Interrupt Flag⁽⁴⁾

Value	Description
1	Interrupt has occurred
0	Interrupt event has not occurred

Bit 3 – I2C1RXIF I2C1 Receive Interrupt Flag⁽⁴⁾

Value	Description
1	Interrupt has occurred
0	Interrupt event has not occurred

Bit 2 – SPI1IF SPI1 Interrupt Flag⁽⁵⁾

Value	Description
1	Interrupt has occurred
0	Interrupt event has not occurred

Bit 1 – SPI1TXIF SPI1 Transmit Interrupt Flag⁽⁶⁾

Value	Description
1	Interrupt has occurred
0	Interrupt event has not occurred

Bit 0 – SPI1RXIF SPI1 Receive Interrupt Flag⁽⁶⁾

Value	Description
1	Interrupt has occurred
0	Interrupt event has not occurred

Interrupt flag bits get set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit. User software must ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. I2C1EIF is a read-only bit. To clear the interrupt condition, all bits in the I2C1ERR register must be cleared. I2C1IF is a read-only bit. To clear the interrupt condition, all bits in the I2C1PIR register must be cleared. I2C1TXIF and I2C1RXIF are read-only bits. To clear the interrupt condition, the CLRBF bit in I2C1STAT1 must be set. SPI1IF is a read-only bit. To clear the interrupt condition, all bits in the SPI1INTF register must be cleared. SPI1TXIF and SPI1RXIF are read-only bits and cannot be set/cleared by software.