11.13.22 PIR5
Note:
- Interrupt flag bits get set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit. User software must ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.
- PWM2IF is a read-only bit. To clear the interrupt condition, all bits in the PWM2GIR register must be cleared.
Name: | PIR5 |
Address: | 0x46E |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
IOCSRIF | CLC4IF | CLC3IF | CLC2IF | CLC1IF | CWG1IF | PWM2IF | PWM2PIF | ||
Access | R | R/W/HS | R/W/HS | R/W/HS | R/W/HS | R/W/HS | R | R/W/HS | |
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 7 – IOCSRIF Signal Routing Ports Interrupt-on-Change Interrupt Flag
Value | Description |
---|---|
1 | Interrupt has occurred (must be cleared by software) |
0 | Interrupt event has not occurred |
Bit 6 – CLC4IF CLC4 Interrupt Flag
Value | Description |
---|---|
1 | Interrupt has occurred (must be cleared by software) |
0 | Interrupt event has not occurred |
Bit 5 – CLC3IF CLC3 Interrupt Flag
Value | Description |
---|---|
1 | Interrupt has occurred (must be cleared by software) |
0 | Interrupt event has not occurred |
Bit 4 – CLC2IF CLC2 Interrupt Flag
Value | Description |
---|---|
1 | Interrupt has occurred (must be cleared by software) |
0 | Interrupt event has not occurred |
Bit 3 – CLC1IF CLC1 Interrupt Flag
Value | Description |
---|---|
1 | Interrupt has occurred (must be cleared by software) |
0 | Interrupt event has not occurred |
Bit 2 – CWG1IF CWG1 Interrupt Flag
Value | Description |
---|---|
1 | Interrupt has occurred (must be cleared by software) |
0 | Interrupt event has not occurred |
Bit 1 – PWM2IF PWM2 Parameter Interrupt Flag(2)
Value | Description |
---|---|
1 | Interrupt has occurred |
0 | Interrupt event has not occurred |
Bit 0 – PWM2PIF PWM2 Period Interrupt Flag
Value | Description |
---|---|
1 | Interrupt has occurred (must be cleared by software) |
0 | Interrupt event has not occurred |