11.13.21 PIR4
Note:
- Interrupt flag bits get set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit. User software must ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.
- PWM1IF is a read-only bit. To clear the interrupt condition, all bits in the PWM1GIR register must be cleared.
Name: | PIR4 |
Address: | 0x46D |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
PWM1IF | PWM1PIF | CCP2IF | CCP1IF | TU16BIF | TU16AIF | TMR4IF | TMR2IF | ||
Access | R | R/W/HS | R/W/HS | R/W/HS | R | R | R/W/HS | R/W/HS | |
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 7 – PWM1IF PWM1 Parameter Interrupt Flag(2)
Value | Description |
---|---|
1 | Interrupt has occurred |
0 | Interrupt event has not occurred |
Bit 6 – PWM1PIF PWM1 Period Interrupt Flag
Value | Description |
---|---|
1 | Interrupt has occurred (must be cleared by software) |
0 | Interrupt event has not occurred |
Bit 5 – CCP2IF CCP2 Interrupt Flag
Value | Description |
---|---|
1 | Interrupt has occurred (must be cleared by software) |
0 | Interrupt event has not occurred |
Bit 4 – CCP1IF CCP1 Interrupt Flag
Value | Description |
---|---|
1 | Interrupt has occurred (must be cleared by software) |
0 | Interrupt event has not occurred |
Bit 3 – TU16BIF 16-bit Universal Timer B Interrupt Flag
Value | Description |
---|---|
1 | Interrupt has occurred (must be cleared by software) |
0 | Interrupt event has not occurred |
Bit 2 – TU16AIF 16-bit Universal Timer A Interrupt Flag
Value | Description |
---|---|
1 | Interrupt has occurred (must be cleared by software) |
0 | Interrupt event has not occurred |
Bit 1 – TMR4IF TMR4 Interrupt Flag
Value | Description |
---|---|
1 | Interrupt has occurred (must be cleared by software) |
0 | Interrupt event has not occurred |
Bit 0 – TMR2IF TMR2 Interrupt Flag
Value | Description |
---|---|
1 | Interrupt has occurred (must be cleared by software) |
0 | Interrupt event has not occurred |