3.4.1 Per-Cycle Accumulated Phase Voltage Quantities
The metrology module generates the following accumulated phase voltage (V2) quantities: CYCLE_V_A, CYCLE_V_B, CYCLE_V_C, CYCLE_V_A_F, CYCLE_V_B_F, and CYCLE_V_C_F.
They are in units of [Volt2samp scaled]. They are scaled accumulated phase voltage quantities in the last line cycle measurement period. They are calculated according to the following formula:
Where,
- V_x_samplei is ith sampled phase voltage value of phase x in present cycle
- x = [A, B, C]
- N = The number of samples in the last line cycle measurement interval
They may be used to calculate the RMS value of phase voltage.
The CYCLE_V_x and CYCLE_V_x_F are stored in the uQ24.40 format.
| Name: | CYCLE_V_A, CYCLE_V_B, CYCLE_V_C, CYCLE_V_A_F, CYCLE_V_B_F, CYCLE_V_C_F |
| Property: | Read |
| Bit | 63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | |
| CYCLE_V_x/CYCLE_V_x_F[63:56] | |||||||||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | |
| CYCLE_V_x/CYCLE_V_x_F[55:48] | |||||||||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | |
| CYCLE_V_x/CYCLE_V_x_F[47:40] | |||||||||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 | |
| CYCLE_V_x/CYCLE_V_x_F[39:32] | |||||||||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| CYCLE_V_x/CYCLE_V_x_F[31:24] | |||||||||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| CYCLE_V_x/CYCLE_V_x_F[23:16] | |||||||||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| CYCLE_V_x/CYCLE_V_x_F[15:8] | |||||||||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CYCLE_V_x/CYCLE_V_x_F[7:0] | |||||||||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
