3.4.2 Per-Cycle Accumulated Voltage Quantities Between Phases
The metrology module generates the following accumulated phase voltage (V2) quantities between phases: CYCLE_V_AB, CYCLE_V_BC, CYCLE_V_CA, CYCLE_V_AB_F, CYCLE_V_BC_F, and CYCLE_V_CA_F.
They are in units of [Volt2samp scaled]. They are scaled accumulated voltage quantities between phases in the last line cycle measurement period. They are calculated according to the following formula:
Where,
- V_x_samplei is ith sampled phase voltage value of phase x in present cycle
- V_y_samplei is ith sampled phase voltage value of phase y in present cycle
- x = [A, B, C]
- y = [B, C, A]
- N = The number of samples in the last line cycle measurement interval
They are used to calculate the RMS value of voltage between phases.
The V_xy and V_xy_F are stored in the uQ24.40 format.
These accumulators are useful for calculating the phase shift between voltages by applying the Law of Cosines. Depending on the application requirements, it can be utilized either the fundamental plus harmonics or the fundamental only, ended in the "_F", registers.
| Name: | CYCLE_V_AB, CYCLE_V_BC, CYCLE_V_CA, CYCLE_V_AB_F, CYCLE_V_BC_F, CYCLE_V_CA_F |
| Property: | Read |
| Bit | 63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | |
| CYCLE_V_xy/CYCLE_V_xy_F[63:56] | |||||||||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | |
| CYCLE_V_xy/CYCLE_V_xy_F[55:48] | |||||||||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | |
| CYCLE_V_xy/CYCLE_V_xy_F[47:40] | |||||||||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 | |
| CYCLE_V_xy/CYCLE_V_xy_F[39:32] | |||||||||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| CYCLE_V_xy/CYCLE_V_xy_F[31:24] | |||||||||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| CYCLE_V_xy/CYCLE_V_xy_F[23:16] | |||||||||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| CYCLE_V_xy/CYCLE_V_xy_F[15:8] | |||||||||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CYCLE_V_xy/CYCLE_V_xy_F[7:0] | |||||||||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |