2.10 PCIe Initialization

To achieve the PCIe initialization requirement, the physical layer is configured using Flash configuration bits. The remaining configuration is done during design initialization with the user data stored in the non-volatile memory.

For resetting the PCIESS, use the PCIe_x_PERST_N sideband reset input.

For resetting PCIESS using drivers, use hot reset (in-band reset). A hot reset is propagated in-band from one link neighbor to another by sending several TS1 (training sequence 1 packets) with bit0 of symbol 5 asserted. These TS1 are sent on all lanes. Once sent, the Tx and Rx of hot reset end up in detect link training state machine (LTSSM) state. Hot reset is initiated by setting the secondary bus reset bit in the root ports bridge control configuration register.

The time taken to complete initialization depends on the number of lanes to be configured and the number of PCI controllers to be configured. When PCIE0 controller is initialized with Libero default values, the PCIE initialization time is 440 µs. When PCIE0 and PCIE1 are both enabled, the PCIE initialization time is 782 µs.

The worst case PCIE initialization time is calculated with all PCIe Controller and Bridge register writes in stage 2 assembly file as listed in the following table.

For more information about the PCIe initialization process, see PolarFire Family PCI Express User Guide.