2.11 State of Blocks During Power-Up

The following table shows the state of different blocks during device power-up.

Table 2-11. Default State During Device Power-Up
BlockPORDevice BootDesign and Memory Initialization State
System ControllerHeld in resetExecuting boot-up sequencePerforms design and memory initialization
sNVMHeld in resetPower up sequence, then functionalFunctional
FPGA fabric arrayPowered downPower up sequence, then functionalFunctional
LSRAMPowered downPowered up, uninitializedInitialized with user data if configured.
µSRAMPowered downPowered up, uninitializedInitialized with user data if configured
µPROMPowered downPowered upFunctional
Math blockPowered downPowered upFunctional
Transceiver and TX PLLsPowered downPowered up but not functional

Termination Optionally Enabled

Initialized with user data and functional
GPIO/HSIO - Low Speed (if power is applied)Input buffers are disabled and output buffers are tristated.

GPIO buffers are in hot-plug mode.

Powered up but not usable

GPIO buffers are in hot-plug mode.

HSIO buffers do not support hot-plug capability

Functional if IO and IO Auxiliary Supplies supply exceeds threshold
GPIO/HSIO - High-speed (if power is applied)Input buffers are disabled and output buffers are tristated.

GPIO buffers are in hot-plug mode.

Powered up but not usable

GPIO buffers are in hot-plug mode.

HSIO buffers do not support hot-plug capability.

Functional at high-speed after the completion of IO calibration if IO and IO Auxiliary Supplies are applied
PCIe®Powered downPowered up but not functional.Initialized with user data and functional
Transceiver I/OTristated and hot-plug modeTristated in hot-plug mode

Termination optionally enabled.

Termination Enabled, operational
MSSIOs (for PolarFire® SoC and RT PolarFire SoC FPGA only)TristatedTristatedTristated
MSS (for PolarFire SoC and RT PolarFire SoC FPGA only)Powered downPowered downPowered down
Important: For more information about cold boot and warm boot power-up to functional time, see the “Power-Up to Functional Timing” section in the respective PolarFire FPGA Datasheet , RT PolarFire FPGA Datasheet , PolarFire SoC FPGA Datasheet , or RT PolarFire SoC FPGA Datasheet .