2.1 Power-On

When the device is powered on, the POR circuitry detects voltage ramp-up on the VDD, VDD18, and VDD25 power supply rails using voltage detectors. For a list of power supplies, see Appendix: Power Supplies. The System Controller remains in the Reset state until the required voltage threshold levels are reached. The System Controller is responsible for enabling or turning on the FPGA fabric and related I/Os.

The voltage detectors in the devices are calibrated with a high level of accuracy to ensure reliable monitoring of minimum threshold levels. For power-supply threshold voltage levels to release POR, see the “Power-on Reset Voltages” section in the respective document: PolarFire FPGA Datasheet , RT PolarFire FPGA Datasheet , PolarFire SoC FPGA Datasheet , or RT PolarFire SoC FPGA Datasheet . The device boot starts after a fixed delay of 10 µs, once the voltage supply rails reach their respective threshold levels.

In the PolarFire family of devices, there are separate voltage detectors to monitor I/O bank supplies. During POR, the dedicated I/O bank is powered up and the serial transceivers and the fabric are powered down. If the VDDI of the banks goes approximately below 0.85V, then, depending on the process, voltage, and temperature (also referred to as PVT) conditions, the HSIO/GPIO banks are tri-stated. Separate detectors in the associated I/O bank controller (for Bank 3) detect when the VDDI3 is at the required level to enable the inputs and subsequently (after a delay of 200 ns) the outputs of the dedicated I/O bank (including SPI configuration and JTAG I/O).

For more information on power supply sequencing requirements and recommendations, see the “Core Power Supply Operations” section, in the respective document: PolarFire FPGA Board Design User Guide, RT PolarFire FPGA Board Design User Guide , or PolarFire SoC Board Design Guidelines User Guide.