2.8 Transceiver Initialization

Transceiver power-up depends on VDDA, VDDA25, and VDD_XCVR_CLK.

VDD_XCVR_CLK is applicable if an external reference clock is used for transceivers. For a list of power supplies, see Appendix: Power Supplies. During power-up, glitches can occur in the reference clocks and the data bits. The transceiver is initialized by the Flash configuration bits and the design initialization client, which is executed from the sNVM.

When XCVR_INIT_DONE/DEVICE_INIT_DONE signal from PF_INIT_MONITOR or PFSOC_INIT_MONITOR goes high, the transceiver is completely configured. The user logic using the XCVR clock must be held in reset until the XCVR_INIT_DONE signal is asserted.

The transceiver data pins are in hot-plug mode at power-up. Programming bits can be used to detect TX and/or RX termination early to enable fast Receiver Detection in standards such as PCI Express.

The time taken to complete the initialization of the transceiver subsystem depends on the number of lanes to be configured and the number of different high-speed serial protocols to be configured. When QUAD0 with 1 Lane is initialized with Libero default values, the XCVR initialization time is 282 µs as listed in the following table. The worst-case delay is calculated with all PCS and PMA register writes in stage 2 assembly file. For information about stage 2, see Design and Memory Initialization.