18.3.5 Truth Table Symbol Descriptions

Combinational truth tables use the following symbols:

• 1 - indicates logic level one
• 0 - indicates logic level zero
• A - indicates internal input port
• NC - indicates not connected
• PAD - indicates external port
• X - indicates either logic level one or zero (don’t care)
• Z - indicates three-state logic level (high resistance)

GLx

This component is supported by A500K, APA families.

• Function: Global Input Buffer. This macro is available with a Schmitt Trigger for APA devices.
• Input: PAD
• Output: GL

Table 18-154. Truth Table

Input	Output
PAD	GL
0	0
1	1

Table 18-155. Tile Usage

Family	I/O Tiles
All listed	2

Table 18-156. Available GLx Macro Types

Name	Description
GL25	2.5 Volt CMOS input levels; not supported in ProASICPLUS (APA)
GL33	3.3 Volt CMOS input levels, PCI compliant
GL25LP	2.5 Volt CMOS input levels, low power
GL25S	2.5 Volt CMOS input levels, Schmitt Trigger; not supported in ProASICPLUS (APA)
GL33S	3.3 Volt CMOS input levels, Schmitt Trigger
GL25LPS	2.5 Volt CMOS input levels, low power, Schmitt Trigger

GLxU

This component is supported by A500K, APA families.

• Function: Global Input Buffer with Pull-up Resistor. This macro is available with a Schmitt Trigger for APA devices.
• Input: PAD
• Output: GL

Table 18-157. Truth Table

Input	Output
PAD	GL
0	0
1	1
NC	1

Table 18-158. Tile Usage

Family	Comb
All listed	2 I/O Tiles

Table 18-159. Available GLxU Macro Types

Name	Description
GL25U	2.5 Volt CMOS input levels, with pull-up resistor; not supported in ProASICPLUS (APA)
GL33U	3.3 Volt CMOS input levels, with pull-up resistor, PCI compliant
GL25LPU	2.5 Volt CMOS input levels, low power, with pull-up resistor
GL25US	2.5 Volt CMOS input levels, with pull-up resistor, Schmitt Trigger; not supported in ProASICPLUS (APA)
GL33US	3.3 Volt CMOS input levels, with pull-up resistor, Schmitt Trigger
GL25LPUS	2.5 Volt CMOS input levels, low power, with pull-up resistor, Schmitt Trigger

GLINT

This component is supported by A500K, APA families.

• Function: Global Buffer with Internal Connection
• Input: A
• Output: GL

Table 18-160. Truth Table

Input	Output
A	GL
1	1
0	0

Table 18-161. Tile Usage

Family	I/O Tiles
All listed	1

GLIBx

This component is supported by A500K, APA families.

• Function: Global Input Buffer with Independent Input Buffer. This macro is available with a Schmitt Trigger for APA devices.
• Input: PAD, A
• Output: Y, GL

Table 18-162. Truth Table

Input	Output	Input	Output
PAD	Y	A	GL
1	1	1	1
0	0	0	0

Table 18-163. Tile Usage

Family	I/O Tiles
All listed	2

Table 18-164. Available Macro Types

Name	Description
GLIB25	2.5 Volt CMOS input levels; not supported in ProASICPLUS (APA)
GLIB33	3.3 Volt CMOS input levels, PCI compliant
GLIB25LP	2.5 Volt CMOS input levels, low power
GLIB25S	2.5 Volt CMOS input levels, Schmitt Trigger; not supported in ProASICPLUS (APA)
GLIB33S	3.3 Volt CMOS input levels, Schmitt Trigger
GLIB25LPS	2.5 Volt CMOS input levels, low power, Schmitt Trigger

GLIBxU

This component is supported by A500K, APA families.

• Function: Global Input Buffer with Independent Input Buffer and Pull-up Resistor. This macro is available with a Schmitt Trigger for APA devices.
• Input: PAD, A
• Output: Y, GL

Table 18-165. Truth Table

Input	Output	Input	Output
PAD	Y	A	GL
1	1	1	1
0	0	0	0
NC	1

Table 18-166. Tile Usage

Family	I/O Tiles
All listed	2

Table 18-167. Available Macro Types

Name	Description
GLIB25U	2.5 Volt CMOS input levels, with pull-up resistor; not supported in ProASICPLUS (APA)
GLIB33U	3.3 Volt CMOS input levels, with pull-up resistor, PCI compliant
GLIB25LPU	2.5 Volt CMOS input levels, low power, with pull-up resistor
GLIB25US	2.5 Volt CMOS input levels, with pull-up resistor and Schmitt Trigger; not supported in ProASICPLUS (APA)
GLIB33US	3.3 Volt CMOS input levels, with pull-up resistor and Schmitt Trigger
GLIB25LPUS	2.5 Volt CMOS input levels, low power, with pull-up resistor and Schmitt Trigger

GLMIBx

This component is supported by A500K, APA families.

• Function: Global Multiplexed Input Buffer. This macro is available with a Schmitt Trigger for APA devices.
• Input: PAD, A, EN
• Output: Y, GL

Table 18-168. Truth Table

Input	Output
PAD	Y
1	1
0	0

Table 18-169. Truth Table

Input			Output
PAD	A	EN	GL
0	X	0	0
1	X	0	1
X	1	1	1
X	0	1	0

Table 18-170. Tile Usage

Family	I/O Tiles
All listed	2

Table 18-171. Available Macro Types

Name	Description
GLMIB25	2.5 Volt CMOS input levels; not supported in ProASICPLUS (APA)
GLMIB33	3.3 Volt CMOS input levels, PCI compliant
GLMIB25LP	2.5 Volt CMOS input levels, low power
GLMIB25S	2.5 Volt CMOS input levels, Schmitt Trigger; not supported in ProASICPLUS (APA)
GLMIB33S	3.3 Volt CMOS input levels, Schmitt Trigger
GLMIB25LPS	2.5 Volt CMOS input levels, low power, Schmitt Trigger

GLMIBxU

This component is supported by A500K, APA families.

• Function: Global Multiplexed Input Buffer with Pull-up Resistor. This macro is available with a Schmitt Trigger for APA devices.
• Input: PAD, A, EN
• Output: Y, GL

Table 18-172. Truth Table

Input	Output
PAD	Y
1	1
0	0
NC	1

Table 18-173. Truth Table

Input			Output
PAD	A	EN	GL
0	X	0	0
1	X	0	1
X	1	1	1
X	0	1	0
NC	X	0	1

Table 18-174. Tile Usage

Family	I/O Tiles
All listed	2

Table 18-175. Available Macro Types

Name	Description
GLMIB25U	2.5 Volt CMOS input levels, with pull-up resistor; not supported in ProASICPLUS (APA)
GLMIB33U	3.3 Volt CMOS input levels, with pull-up resistor, PCI compliant
GLMIB25LPU	2.5 Volt CMOS input levels, low power, with pull-up resistor
GLMIB25US	2.5 Volt CMOS input levels, with pull-up resistor and Schmitt Trigger; not supported in ProASICPLUS (APA)
GLMIB33US	3.3 Volt CMOS input levels, with pull-up resistor and Schmitt Trigger
GLMIB25LPUS	2.5 Volt CMOS input levels, low power, with pull-up resistor and Schmitt Trigger

GLMIBLx

This component is supported by A500K, APA families.

• Function: Global Multiplexed Input Buffer with Active Low Enable; this macro is available with a Schmitt Trigger for APA devices.
• Input: PAD, A, EN
• Output: Y, GL

Table 18-176. Truth Table

Input	Output
PAD	Y
1	1
0	0

Table 18-177. Truth Table

Input			Output
PAD	A	EN	GL
X	0	0	0
X	1	0	1
1	X	1	1
0	X	1	0

Table 18-178. Tile Usage

Family	I/O Tiles
All listed	2

Table 18-179. Available Macro Types

Name	Description
GLMIBL25	2.5 Volt CMOS input levels; not supported in ProASICPLUS (APA)
GLMIBL33	3.3 Volt CMOS input levels, PCI compliant
GLMIBL25LP	2.5 Volt CMOS input levels, low power
GLMIBL25S	2.5 Volt CMOS input levels, Schmitt Trigger; not supported in ProASICPLUS (APA)
GLMIBL33S	3.3 Volt CMOS input levels, Schmitt Trigger
GLMIBL25LPS	2.5 Volt CMOS input levels, low power, Schmitt Trigger

GLMIBLxU

This component is supported by A500K, APA families.

• Function: Global Multiplexed Input Buffer with Active Low Enable and Pull-up Resistor. This macro is available with a Schmitt Trigger for APA devices.
• Input: PAD, A, EN
• Output: Y, GL

Table 18-180. Truth Table

Input	Output
PAD	Y
0	0
1	1
NC	1

Table 18-181. Truth Table

Input			Output
PAD	A	EN	GL
X	0	0	0
X	1	0	1
1	X	1	1
0	X	1	0
NC	X	1	1

Table 18-182. Tile Usage

Family	I/O Tiles
All listed	2

Table 18-183. Available Macro Types

Name	Description
GLMIBL25U	2.5 Volt CMOS input levels, with pull-up resistor; not supported in ProASICPLUS (APA)
GLMIBL33U	3.3 Volt CMOS input levels, with pull-up resistor, PCI compliant
GLMIBL25LPU	2.5 Volt CMOS input levels, low power, with pull-up resistor
GLMIBL25US	2.5 Volt CMOS input levels, with pull-up resistor and Schmitt Trigger; not supported in ProASICPLUS (APA)
GLMIBL33US	3.3 Volt CMOS input levels, with pull-up resistor and Schmitt Trigger
GLMIBL25LPUS	2.5 Volt CMOS input levels, low power, with pull-up resistor and Schmitt Trigger

IBx

This component is supported by A500K, APA families.

• Function: Input Buffer. This macro is available with a Schmitt Trigger for APA devices. I/O macros which have *25LP* require VDDP of 2.5V, while *33* and *25* (no LP) require VDDP of 3.3V.
• Input: PAD
• Output: Y

Table 18-184. Truth Table

Input	Output
PAD	Y
0	0
1	1

Table 18-185. Tile Usage

Family	I/O Tiles
All listed	1

Table 18-186. Available Macro Types

Name	Description
IB25	2.5 Volt CMOS input levels; not supported in ProASICPLUS (APA)
IB33	3.3 Volt CMOS input levels, PCI compliant
IB25LP	2.5 Volt CMOS input levels, low power
IB25S	2.5 Volt CMOS input levels, Schmitt Trigger; not supported in ProASICPLUS (APA)
IB33S	3.3 Volt CMOS input levels, PCI compliant, Schmitt Trigger
IB25LPS	2.5 Volt CMOS input levels, low power, Schmitt Trigger

IBxU

This component is supported by A500K, APA families.

• Function: Input Buffer with Pull-up Resistor. This macro is available with a Schmitt Trigger for APA devices. I/O macros which have *25LP* require VDDP of 2.5V, while *33* and *25* (no LP) require VDDP of 3.3V.
• Input: PAD
• Output: Y

Table 18-187. Truth Table

Input	Output
PAD	Y
0	0
1	1
NC	1

Table 18-188. Tile Usage

Family	I/O Tiles
All listed	1

Table 18-189. Available Macro Types

Name	Description
IB25U	2.5 Volt CMOS input levels, with pull-up resistor; not supported in ProASICPLUS (APA)
IB33U	3.3 Volt CMOS input levels, with pull-up resistor, PCI compliant
IB25LPU	2.5 Volt CMOS input levels, low power, with pull-up resistor
IB25US	2.5 Volt CMOS input levels, with pull-up resistor and Schmitt Trigger; not supported in ProASICPLUS (APA)
IB33US	3.3 Volt CMOS input levels, with pull-up resistor and Schmitt Trigger
IB25LPUS	2.5 Volt CMOS input levels, low power, with pull-up resistor and Schmitt Trigger

IOB25x

This component is supported by A500K family.

• Function: Bi-Directional Buffer; I/O macros that have *33* and *25* (no LP) require VDDP of 3.3V.
• Input: EN, A, PAD
• Output: PAD, Y

Table 18-190. Truth Table

Input			Output
EN	A	PAD	PAD	Y
1	X	X	A	A
0	X	X	X	PAD

Table 18-191. Tile Usage

Family	I/O Tiles
All listed	1

Table 18-192. Available Macro Types

Name	Description
IOB25HH	2.5 Volt CMOS input levels, high drive strength, high slew rate
IOB25HL	2.5 Volt CMOS input levels, high drive strength, low slew rate
IOB25HN	2.5 Volt CMOS input levels, high drive strength, normal slew rate
IOB25LH	2.5 Volt CMOS input levels, low drive strength, high slew rate
IOB25LL	2.5 Volt CMOS input levels, low drive strength, low slew rate
IOB25LN	2.5 Volt CMOS input levels, low drive strength, normal slew rate

IOB25xU

This component is supported by A500K family.

• Function: Bi-Directional Buffer with Pull-up Resistor; I/O macros that have *25LP* require VDDP of 2.5V.
• Input: EN, A, PAD
• Output: PAD, Y

Table 18-193. Truth Table

Input			Output
EN	A	PAD	PAD	Y
1	X	X	A	A
0	X	X	X	PAD
0	X	NC	NC	1

Table 18-194. Tile Usage

Family	I/O Tiles
All listed	1

Table 18-195. Available Macro Types

Name	Description
IOB25HHU	2.5 Volt CMOS input levels, high drive strength, high slew rate, with pull-up resistor
IOB25HLU	2.5 Volt CMOS input levels, high drive strength, low slew rate, with pull-up resistor
IOB25HNU	2.5 Volt CMOS input levels, high drive strength, normal slew rate, with pull-up resistor
IOB25LHU	2.5 Volt CMOS input levels, low drive strength, high slew rate, with pull-up resistor
IOB25LLU	2.5 Volt CMOS input levels, low drive strength, low slew rate, with pull-up resistor
IOB25LNU	2.5 Volt CMOS input levels, low drive strength, normal slew rate, with pull-up resistor

IOB25LPx

This component is supported by A500K, APA families.

• Function: Bi-Directional Buffer (Low Power); I/O macros that have *25LP* require VDDP of 2.5V.
• Input: EN, A, PAD
• Output: PAD, Y

Table 18-196. Truth Table

Input			Output
EN	A	PAD	PAD	Y
1	X	X	A	A
0	X	X	X	PAD

Table 18-197. Tile Usage

Family	I/O Tiles
All listed	1

Table 18-198. Available Macro Types

Name	Description
IOB25LPHH	2.5 Volt CMOS input levels, low power, high drive strength, high slew rate
IOB25LPHL	2.5 Volt CMOS input levels, low power, high drive strength, low slew rate
IOB25LPHN	2.5 Volt CMOS input levels, low power, high drive strength, normal slew rate
IOB25LPLH	2.5 Volt CMOS input levels, low power, low drive strength, high slew rate
IOB25LPLL	2.5 Volt CMOS input levels, low power, low drive strength, low slew rate
IOB25LPLN	2.5 Volt CMOS input levels, low power, low drive strength, normal slew rate

IOB25LPxU

This component is supported by A500K, APA families.

• Function: Bi-Directional Buffer with Low Power and Pull-up Resistor; I/O macros that have *25LP* require VDDP of 2.5V.
• Input: EN, A, PAD
• Output: PAD, Y

Table 18-199. Truth Table

Input			Output
EN	A	PAD	PAD	Y
1	X	X	A	A
0	X	X	X	PAD
0	X	NC	NC	1

Table 18-200. Tile Usage

Family	I/O Tiles
All listed	1

Table 18-201. Available Macro Types

Name	Description
IOB25LPHHU	2.5 Volt CMOS input levels, low power, high drive strength, high slew rate, with pull-up resistor
IOB25LPHLU	2.5 Volt CMOS input levels, low power, high drive strength, low slew rate, with pull-up resistor
IOB25LPHNU	2.5 Volt CMOS input levels, low power, high drive strength, normal slew rate, with pull-up resistor
IOB25LPLHU	2.5 Volt CMOS input levels, low power, low drive strength, high slew rate, with pull-up resistor
IOB25LPLLU	2.5 Volt CMOS input levels, low power, low drive strength, low slew rate, with pull-up resistor
IOB25LPLNU	2.5 Volt CMOS input levels, low power, low drive strength, normal slew rate, with pull-up resistor

IOB33x

This component is supported by A500K, APA families.

• Function: Bi-Directional Buffer; I/O macros that have *33* and *25* (no LP) require VDDP of 3.3V.
• Input: EN, A, PAD
• Output: PAD, Y

Table 18-202. Truth Table

Input			Output
EN	A	PAD	PAD	Y
1	X	X	A	A
0	X	X	X	PAD

Table 18-203. Tile Usage

Family	I/O Tiles
All listed	1

Table 18-204. Available Macro Types

Name	Description
IOB33LH	3.3 Volt CMOS input levels, low strength drive, high slew rate
IOB33LL	3.3 Volt CMOS input levels, low strength drive, low slew rate
IOB33LN	3.3 Volt CMOS input levels, low strength drive, normal slew rate
IOB33PH	3.3 Volt CMOS input levels, PCI compliant, high slew rate
IOB33PL	3.3 Volt CMOS input levels, PCI compliant, low slew rate
IOB33PN	3.3 Volt CMOS input levels, normal slew rate

IOB33xU

This component is supported by A500K, APA families.

• Function: Bi-Directional Buffer with Pull-up Resistor; I/O macros that have *33* and *25* (no LP) require VDDP of 3.3V.
• Input: EN, A, PAD
• Output: PAD, Y

Table 18-205. Truth Table

Input			Output
EN	A	PAD	PAD	Y
1	X	X	A	A
0	X	X	X	PAD
0	X	NC	NC	1

Table 18-206. Tile Usage

Family	I/O Tiles
All listed	1

Table 18-207. Available Macro Types

Name	Description
IOB33LHU	3.3 Volt CMOS input levels, low strength drive, high slew rate, with pull-up resistor
IOB33LLU	3.3 Volt CMOS input levels, low strength drive, low slew rate, with pull-up resistor
IOB33LNU	3.3 Volt CMOS input levels, low strength drive, normal slew rate, with pull-up resistor
IOB33PHU	3.3 Volt CMOS input levels, PCI compliant, high slew rate, with pull-up resistor
IOB33PLU	3.3 Volt CMOS input levels, low slew rate, with pull-up resistor
IOB33PNU	3.3 Volt CMOS input levels, normal slew rate, with pull-up resistor

IOBL25x

This component is supported by A500K family.

• Function: Bi-Directional Buffer with Active Low Enable; I/O macros that have *25* (no LP) require VDDP of 3.3V.
• Input: EN, A, PAD
• Output: PAD, Y

Table 18-208. Truth Table

Input			Output
EN	A	PAD	PAD	Y
1	X	X	X	PAD
0	X	X	A	A

Table 18-209. Tile Usage

Family	I/O Tiles
All listed	1

Table 18-210. Available Macro Types

Name	Description
IOBL25HH	2.5 Volt CMOS input levels, high drive strength, high slew rate
IOBL25HL	2.5 Volt CMOS input levels, high drive strength, low slew rate
IOBL25HN	2.5 Volt CMOS input levels, high drive strength, normal slew rate
IOBL25LH	2.5 Volt CMOS input levels, low drive strength, high slew rate
IOBL25LL	2.5 Volt CMOS input levels, low drive strength, low slew rate
IOBL25LN	2.5 Volt CMOS input levels, low drive strength, normal slew rate

IOBL25xU

This component is supported by A500K family.

• Function: Bi-Directional Buffer with Active Low Enable and Pull-up Resistor; I/O macros that have *25* (no LP) require VDDP of 3.3V.
• Input: EN, A, PAD
• Output: PAD, Y

Table 18-211. Truth Table

Input			Output
EN	A	PAD	PAD	Y
1	X	X	X	PAD
0	X	X	A	A
1	X	NC	NC	1

Table 18-212. Tile Usage

Family	I/O Tiles
All listed	1

Table 18-213. Available Macro Types

Name	Description
IOBL25HHU	2.5 Volt CMOS input levels, high drive strength, high slew rate, with pull-up resistor
IOBL25HLU	2.5 Volt CMOS input levels, high drive strength, low slew rate, with pull-up resistor
IOBL25HNU	2.5 Volt CMOS input levels, high drive strength, normal slew rate, with pull-up resistor
IOBL25LHU	2.5 Volt CMOS input levels, low drive strength, high slew rate, with pull-up resistor
IOBL25LLU	2.5 Volt CMOS input levels, low drive strength, low slew rate, with pull-up resistor
IOBL25LNU	2.5 Volt CMOS input levels, low drive strength, normal slew rate, with pull-up resistor

IOBL25LPx

This component is supported by A500K, APA families.

• Function: Bi-Directional Buffer with Active Low Enable (Low Power); I/O macros that have *25LP* require VDDP of 2.5V.
• Input: EN, A, PAD
• Output: PAD, Y

Table 18-214. Truth Table

Input			Output
EN	A	PAD	PAD	Y
1	X	X	X	PAD
0	X	X	A	A

Table 18-215. Tile Usage

Family	I/O Tiles
All listed	1

Table 18-216. Available Macro Types

Name	Description
IOBL25LPHH	2.5 Volt CMOS input levels, low power, high drive strength, high slew rate
IOBL25LPHL	2.5 Volt CMOS input levels, low power, high drive strength, low slew rate
IOBL25LPHN	2.5 Volt CMOS input levels, low power, high drive strength, normal slew rate
IOBL25LPLH	2.5 Volt CMOS input levels, low power, low drive strength, high slew rate
IOBL25LPLL	2.5 Volt CMOS input levels, low power, low drive strength, low slew rate
IOBL25LPLN	2.5 Volt CMOS input levels, low power, low drive strength, normal slew rate

IOBL25LPxU

This component is supported by A500K, APA families.

• Function: Bi-Directional Buffer with Active Low Enable, Low Power, and Pull-up Resistor; I/O macros that have *25LP* require VDDP of 2.5V.
• Input: EN, A, PAD
• Output: PAD, Y

Table 18-217. Truth Table

Input			Output
EN	A	PAD	PAD	Y
1	X	X	X	PAD
0	X	X	A	A
1	X	NC	NC	1

Table 18-218. Tile Usage

Family	I/O Tiles
All listed	1

Table 18-219. Available Macro Types

Name	Description
IOBL25LPHHU	2.5 Volt CMOS input levels, low power, high drive strength, high slew rate, with pull-up resistor
IOBL25LPHLU	2.5 Volt CMOS input levels, low power, high drive strength, low slew rate, with pull-up resistor
IOBL25LPHNU	2.5 Volt CMOS input levels, low power, high drive strength, normal slew rate, with pull-up resistor
IOBL25LPLHU	2.5 Volt CMOS input levels, low power, low drive strength, high slew rate, with pull-up resistor
IOBL25LPLLU	2.5 Volt CMOS input levels, low power, low drive strength, low slew rate, with pull-up resistor
IOBL25LPLNU	2.5 Volt CMOS input levels, low power, low drive strength, normal slew rate, with pull-up resistor

IOBL33x

This component is supported by A500K, APA families.

• Function: Bi-Directional Buffer with Active Low Enable; I/O macros that have *33* and *25* (no LP) require VDDP of 3.3V.
• Input: EN, PAD, A
• Output: PAD, Y

Table 18-220. Truth Table

Input			Output
EN	A	PAD	PAD	Y
1	X	X	X	PAD
0	X	X	A	A

Table 18-221. Tile Usage

Family	I/O Tiles
All listed	1

Table 18-222. Available Macro Types

Name	Description
IOBL33LH	3.3 Volt CMOS input levels, low strength drive, high slew rate
IOBL33LL	3.3 Volt CMOS input levels, low strength drive, low slew rate
IOBL33LN	3.3 Volt CMOS input levels, low strength drive, normal slew rate
IOBL33PH	3.3 Volt CMOS input levels, PCI compliant, high slew rate
IOBL33PL	3.3 Volt CMOS input levels, PCI compliant, low slew rate
IOBL33PN	3.3 Volt CMOS input levels, PCI compliant, normal slew rate

IOBL33xU

This component is supported by A500K, APA families.

• Function: Bi-Directional Buffer with Active Low Enable and Pull-up Resistor; I/O macros that have *33* (no LP) require VDDP of 3.3V.
• Input: EN, PAD, A
• Output: PAD, Y

Table 18-223. Truth Table

Input			Output
EN	A	PAD	PAD	Y
1	X	X	X	PAD
0	X	X	A	A
1	X	NC	NC	1

Table 18-224. Tile Usage

Family	I/O Tiles
All listed	1

Table 18-225. Available Macro Types

Name	Description
IOBL33LHU	3.3 Volt CMOS input levels, low strength drive, high slew rate, with pull-up resistor
IOBL33LLU	3.3 Volt CMOS input levels, low strength drive, low slew rate, with pull-up resistor
IOBL33LNU	3.3 Volt CMOS input levels, low strength drive, normal slew rate, with pull-up resistor
IOBL33PHU	3.3 Volt CMOS input levels, PCI compliant, high slew rate, with pull-up resistor
IOBL33PLU	3.3 Volt CMOS input levels, PCI compliant, low slew rate, with pull-up resistor
IOBL33PNU	3.3 Volt CMOS input levels, PCI compliant, normal slew rate, with pull-up resistor

OB25x

This component is supported by A500K family.

• Function: Output Buffer
• Input: A
• Output: PAD

Table 18-226. Truth Table

Input	Output
A	PAD
0	0
1	1

Table 18-227. Tile Usage

Family	I/O Tiles
All listed	1

Table 18-228. Available Macro Types

Name	Description
OB25HH	2.5 Volt CMOS input levels, high strength drive, high slew rate
OB25HL	2.5 Volt CMOS input levels, high strength drive, low slew rate
OB25HN	2.5 Volt CMOS input levels, high strength drive, normal slew rate
OB25LH	2.5 Volt CMOS input levels, low strength drive, high slew rate
OB25LL	2.5 Volt CMOS input levels, low strength drive, low slew rate
OB25LN	2.5 Volt CMOS input levels, low strength drive, normal slew rate

OB25LPx

This component is supported by A500K, APA families.

• Function: Output Buffer (Low Power)
• Input: A
• Output: PAD

Table 18-229. Truth Table

Input	Output
A	PAD
0	0
1	1

Table 18-230. Tile Usage

Family	I/O Tiles
All listed	1

Table 18-231. Available Macro Types

Name	Description
OB25LPHH	2.5 Volt CMOS input levels, low power, high strength drive, high slew rate
OB25LPHL	2.5 Volt CMOS input levels, low power, high strength drive, low slew rate
OB25LPHN	2.5 Volt CMOS input levels, low power, high strength drive, normal slew rate
OB25LPLH	2.5 Volt CMOS input levels, low power, low strength drive, high slew rate
OB25LPLL	2.5 Volt CMOS input levels, low power, low strength drive, low slew rate
OB25LPLN	2.5 Volt CMOS input levels, low power, low strength drive, normal slew rate

OB33x

This component is supported by A500K, APA families.

• Function: Output Buffer
• Input: A
• Output: PAD

Table 18-232. Truth Table

Input	Output
A	PAD
0	0
1	1

Table 18-233. Tile Usage

Family	I/O Tiles
All listed	1

Table 18-234. Available Macro Types

Name	Description
OB33LH	3.3 Volt CMOS input levels, low strength drive, high slew rate
OB33LL	3.3 Volt CMOS input levels, low strength drive, low slew rate
OB33LN	3.3 Volt CMOS input levels, low strength drive, normal slew rate
OB33PH	3.3 Volt CMOS input levels, PCI compliant, high slew rate
OB33PL	3.3 Volt CMOS input levels, low slew rate
OB33PN	3.3 Volt CMOS input levels, normal slew rate

OTB25x

This component is supported by A500K family.

• Function: Three State Output Buffer
• Input: EN, A
• Output: PAD

Table 18-235. Truth Table

Input		Output
EN	A	PAD
0	X	Z
1	1	1
1	0	0

Table 18-236. Tile Usage

Family	I/O Tiles
All listed	1

Table 18-237. Available Macro Types

Name	Description
OTB25HH	2.5 Volt CMOS input levels, high strength drive, high slew rate
OTB25HL	2.5 Volt CMOS input levels, high strength drive, low slew rate
OTB25HN	2.5 Volt CMOS input levels, high strength drive, normal slew rate
OTB25LH	2.5 Volt CMOS input levels, low strength drive, high slew rate
OTB25LL	2.5 Volt CMOS input levels, low strength drive, low slew rate
OTB25LN	2.5 Volt CMOS input levels, low strength drive, normal slew rate

OTB25LPx

This component is supported by A500K, APA families.

• Function: Three State Output Buffer (Low Power)
• Input: EN, A
• Output: PAD

Table 18-238. Truth Table

EN	A	PAD
0	X	Z
1	1	1
1	0	0

Table 18-239. Tile Usage

Family	I/O Tiles
All listed	1

Table 18-240. Available Macro Types

Name	Description
OTB25LPHH	2.5 Volt CMOS input levels, low power, high strength drive, high slew rate
OTB25LPHL	2.5 Volt CMOS input levels, low power, high strength drive, low slew rate
OTB25LPHN	2.5 Volt CMOS input levels, low power, high strength drive, normal slew rate
OTB25LPLH	2.5 Volt CMOS input levels, low power, low strength drive, high slew rate
OTB25LPLL	2.5 Volt CMOS input levels, low power, low strength drive, low slew rate
OTB25LPLN	2.5 Volt CMOS input levels, low power, low strength drive, normal slew rate

OTB33x

This component is supported by A500K, APA families.

• Function: Three State Output Buffer
• Input: EN, A
• Output: PAD

Table 18-241. Truth Table

Input		Output
EN	A	PAD
0	X	Z
1	1	1
1	0	0

Table 18-242. Tile Usage

Family	I/O Tiles
All listed	1

Table 18-243. Available Macro Types

Name	Description
OTB33LH	3.3 Volt CMOS input levels, low strength drive, high slew rate
OTB33LL	3.3 Volt CMOS input levels, low strength drive, low slew rate
OTB33LN	3.3 Volt CMOS input levels, low strength drive, normal slew rate
OTB33PH	3.3 Volt CMOS input levels, PCI compliant, high slew rate
OTB33PL	3.3 Volt CMOS input levels, PCI compliant, low slew rate
OTB33PN	3.3 Volt CMOS input levels, PCI compliant, normal slew rate

OTBL25x

This component is supported by A500K family.

• Function: Three State Output Buffer with Active Low Enable
• Input: EN, A
• Output: PAD

Table 18-244. Truth Table

Input		Output
EN	A	PAD
0	0	0
0	1	1
1	X	Z

Table 18-245. Tile Usage

Family	I/O Tiles
All listed	1

Table 18-246. Available Macro Types

Name	Description
OTBL25HH	2.5 Volt CMOS input levels, high strength drive, high slew rate
OTBL25HL	2.5 Volt CMOS input levels, high strength drive, low slew rate
OTBL25HN	2.5 Volt CMOS input levels, high strength drive, normal slew rate
OTBL25LH	2.5 Volt CMOS input levels, low strength drive, high slew rate
OTBL25LL	2.5 Volt CMOS input levels, low strength drive, low slew rate
OTBL25LN	2.5 Volt CMOS input levels, low strength drive, normal slew rate

OTBL25LPx

This component is supported by A500K, APA families.

• Function: Three State Output Buffer with Active Low Enable
• Input: EN, A
• Output: PAD

Table 18-247. Truth Table

Input		Output
EN	A	PAD
0	0	0
0	1	1
1	X	Z

Table 18-248. Tile Usage

Family	I/O Tiles
All listed	1

Table 18-249. Available Macro Types

Name	Description
OTBL25LPHH	2.5 Volt CMOS input levels, low power, high strength drive, high slew rate
OTBL25LPHL	2.5 Volt CMOS input levels, low power, high strength drive, low slew rate
OTBL25LPHN	2.5 Volt CMOS input levels, low power, high strength drive, normal slew rate
OTBL25LPLH	2.5 Volt CMOS input levels, low power, low strength drive, high slew rate
OTBL25LPLL	2.5 Volt CMOS input levels, low power, low strength drive, low slew rate
OTBL25LPLN	2.5 Volt CMOS input levels, low power, low strength drive, normal slew rate

OTBL33x

This component is supported by A500K, APA families.

• Function: Three State Output Buffer with Active Low Enable
• Input: EN, A
• Output: PAD

Table 18-250. Truth Table

Input		Output
EN	A	PAD
0	0	0
0	1	1
1	X	Z

Table 18-251. Tile Usage

Family	I/O Tiles
All listed	1

Table 18-252. Available Macro Types

Name	Description
OTBL33LH	3.3 Volt CMOS input levels, low strength drive, high slew rate
OTBL33LL	3.3 Volt CMOS input levels, low strength drive, low slew rate
OTBL33LN	3.3 Volt CMOS input levels, low strength drive, normal slew rate
OTBL33PH	3.3 Volt CMOS input levels, PCI compliant, high slew rate
OTBL33PL	3.3 Volt CMOS input levels, PCI compliant, low slew rate
OTBL33PN	3.3 Volt CMOS input levels, PCI compliant, normal slew rate

GLMIOBx

This component is supported by APA family.

• Function: Bi-directional IO buffer and global connection
• Input: DE, D, PAD, A, EN
• Output: PAD, Y, GL

Table 18-253. Truth Table

Input					Output
DE	D	PAD	A	EN	PAD	Y	GL
1	X	N/A	X	0	D	D	D
1	X	N/A	X	1	D	D	A
0	X	X	X	0	N/A	PAD	PAD
0	X	X	X	1	N/A	PAD	A

Table 18-254. Tile Usage

Family	I/O Tiles
All listed	1

Table 18-255. Available Macro Types

Name	Description
GLMIOB25LPLU	2.5 Volt CMOS input levels, low power, low strength, low slew, w/ pull-up resistor
GLMIOB25LPL	2.5 Volt CMOS input levels, low power, low strength, low slew
GLMIOB25LPNU	2.5 Volt CMOS input levels, low power, low strength, normal slew, w/ pull-up resistor
GLMIOB25LPN	2.5 Volt CMOS input levels, low power, low strength, normal slew
GLMIOB25LPHU	2.5 Volt CMOS input levels, low power, low strength, high slew, w/ pull-up resistor
GLMIOB25LPH	2.5 Volt CMOS input levels, low power, low strength, high slew
GLMIOB25LPHLU	2.5 Volt CMOS input levels, low power, high strength, low slew, w/ pull-up resistor
GLMIOB25LPHL	2.5 Volt CMOS input levels, low power, high strength, low slew
GLMIOB25LPHNU	2.5 Volt CMOS input levels, low power, high strength, normal slew, w/ pull-up resistor
GLMIOB25LPHN	2.5 Volt CMOS input levels, low power, high strength, normal slew
GLMIOB25LPHHU	2.5 Volt CMOS input levels, low power, high strength, high slew, w/ pull-up resistor
GLMIOB25LPHH	2.5 Volt CMOS input levels, low power, high strength, high slew
GLMIOB33LLU	3.3 Volt CMOS input levels, low power, low slew, w/ pull-up resistor
GLMIOB33LL	3.3 Volt CMOS input levels, low power, low slew
GLMIOB33LNU	3.3 Volt CMOS input levels, low power, normal slew, w/ pull-up resistor
GLMIOB33LN	3.3 Volt CMOS input levels, low power, normal slew
GLMIOB33LHU	3.3 Volt CMOS input levels, low power, high slew, w/ pull-up resistor
GLMIOB33LH	3.3 Volt CMOS input levels, low power, high slew
GLMIOB33PLU	3.3 Volt CMOS input levels, PCI compliant, low slew, w/ pull-up resistor
GLMIOB33PL	3.3 Volt CMOS input levels, PCI compliant, low slew
GLMIOB33PNU	3.3 Volt CMOS input levels, PCI compliant, normal slew, w/ pull-up resistor
GLMIOB33PN	3.3 Volt CMOS input levels, PCI compliant, normal slew
GLMIOB33PHU	3.3 Volt CMOS input levels, PCI compliant, high slew, w/ pull-up resistor
GLMIOB33PH	3.3 Volt CMOS input levels, PCI compliant, high slew

GLMIOBLx

This component is supported by APA family.

• Function: Bi-directional IO buffer and global connection, with active low enable
• Input: DE, D, PAD, A, EN
• Output: PAD, Y, GL

Table 18-256. Truth Table

Input					Output
DE	D	PAD	A	EN	PAD	Y	GL
1	X	N/A	X	0	D	D	A
1	X	N/A	X	1	D	D	D
0	X	X	X	0	N/A	PAD	A
0	X	X	X	1	N/A	PAD	PAD

Table 18-257. Tile Usage

Family	I/O Tiles
All listed	2

Table 18-258. Available Macro Types

Name	Description
GLMIOBL25LPLU	2.5 Volt CMOS input levels, low power, low strength, low slew, w/ pull-up resistor
GLMIOBL25LPL	2.5 Volt CMOS input levels, low power, low strength, low slew
GLMIOBL25LPNU	2.5 Volt CMOS input levels, low power, low strength, normal slew, w/ pull-up resistor
GLMIOBL25LPN	2.5 Volt CMOS input levels, low power, low strength, normal slew
GLMIOBL25LPHU	2.5 Volt CMOS input levels, low power, low strength, high slew, w/ pull-up resistor
GLMIOBL25LPH	2.5 Volt CMOS input levels, low power, low strength, high slew
GLMIOBL25LPHLU	2.5 Volt CMOS input levels, low power, high strength, low slew, w/ pull-up resistor
GLMIOBL25LPHL	2.5 Volt CMOS input levels, low power, high strength, low slew
GLMIOBL25LPHNU	2.5 Volt CMOS input levels, low power, high strength, normal slew, w/ pull-up resistor
GLMIOBL25LPHN	2.5 Volt CMOS input levels, low power, high strength, normal slew
GLMIOBL25LPHHU	2.5 Volt CMOS input levels, low power, high strength, high slew, w/ pull-up resistor
GLMIOBL25LPHH	2.5 Volt CMOS input levels, low power, high strength, high slew
GLMIOBL33LLU	3.3 Volt CMOS input levels, low power, low slew, w/ pull-up resistor
GLMIOBL33LL	3.3 Volt CMOS input levels, low power, low slew
GLMIOBL33LNU	3.3 Volt CMOS input levels, low power, normal slew, w/ pull-up resistor
GLMIOBL33LN	3.3 Volt CMOS input levels, low power, normal slew
GLMIOBL33LHU	3.3 Volt CMOS input levels, low power, high slew, w/ pull-up resistor
GLMIOBL33LH	3.3 Volt CMOS input levels, low power, high slew
GLMIOBL33PLU	3.3 Volt CMOS input levels, PCI compliant, low slew, w/ pull-up resistor
GLMIOBL33PL	3.3 Volt CMOS input levels, PCI compliant, low slew
GLMIOBL33PNU	3.3 Volt CMOS input levels, PCI compliant, normal slew, w/ pull-up resistor
GLMIOBL33PN	3.3 Volt CMOS input levels, PCI compliant, normal slew
GLMIOBL33PHU	3.3 Volt CMOS input levels, PCI compliant, high slew, w/ pull-up resistor
GLMIOBL33PH	3.3 Volt CMOS input levels, PCI compliant, high slew

GLMXx

This component is supported by APA family.

• Function: Two bi-directional IO pads (global and regular), multiplexed
• Input: DE1, D1, PAD1, DE2, D2, PAD2, EN
• Output: PAD1, Y1, PAD2, Y2, GL

Table 18-259. Truth Table

Input							Output
DE1	D1	PAD1	DE2	D2	PAD2	EN	PAD1	Y1	PAD2	Y2	GL
1	X	N/A	1	X	N/A	1	D1	D1	D2	D2	D2
1	X	N/A	1	X	N/A	0	D1	D1	D2	D2	D1
0	X	X	0	X	X	0	N/A	PAD1	N/A	PAD2	PAD1
0	X	X	0	X	X	1	N/A	PAD1	N/A	PAD2	PAD2
1	X	N/A	0	X	X	0	D1	D1	N/A	PAD2	D1
1	X	N/A	0	X	X	1	D1	D1	N/A	PAD2	PAD2
0	X	X	1	X	N/A	0	N/A	PAD1	D2	D2	PAD1
0	X	X	1	X	N/A	1	N/A	PAD1	D2	D2	D2

Table 18-260. Tile Usage

Family	I/O Tiles
All listed	3

Table 18-261. Available Macro Types

Name	Description
GLMX25LPLU	2.5 Volt CMOS input levels, low power, low strength, low slew, w/ pull-up resistor
GLMX25LPL	2.5 Volt CMOS input levels, low power, low strength, low slew
GLMX25LPNU	2.5 Volt CMOS input levels, low power, low strength, normal slew, w/ pull-up resistor
GLMX25LPN	2.5 Volt CMOS input levels, low power, low strength, normal slew
GLMX25LPHU	2.5 Volt CMOS input levels, low power, low strength, high slew, w/ pull-up resistor
GLMX25LPH	2.5 Volt CMOS input levels, low power, low strength, high slew
GLMX25LPHLU	2.5 Volt CMOS input levels, low power, high strength, low slew, w/ pull-up resistor
GLMX25LPHL	2.5 Volt CMOS input levels, low power, high strength, low slew
GLMX25LPHNU	2.5 Volt CMOS input levels, low power, high strength, normal slew, w/ pull-up resistor
GLMX25LPHN	2.5 Volt CMOS input levels, low power, high strength, normal slew
GLMX25LPHHU	2.5 Volt CMOS input levels, low power, high strength, high slew, w/ pull-up resistor
GLMX25LPHH	2.5 Volt CMOS input levels, low power, high strength, high slew
GLMX33LLU	3.3 Volt CMOS input levels, low power, low slew, w/ pull-up resistor
GLMX33LL	3.3 Volt CMOS input levels, low power, low slew
GLMX33LNU	3.3 Volt CMOS input levels, low power, normal slew, w/ pull-up resistor
GLMX33LN	3.3 Volt CMOS input levels, low power, normal slew
GLMX33LHU	3.3 Volt CMOS input levels, low power, high slew, w/ pull-up resistor
GLMX33LH	3.3 Volt CMOS input levels, low power, high slew
GLMX33PLU	3.3 Volt CMOS input levels, PCI compliant, low slew, w/ pull-up resistor
GLMX33PL	3.3 Volt CMOS input levels, PCI compliant, low slew
GLMX33PNU	3.3 Volt CMOS input levels, PCI compliant, normal slew, w/ pull-up resistor
GLMX33PN	3.3 Volt CMOS input levels, PCI compliant, normal slew
GLMX33PHU	3.3 Volt CMOS input levels, PCI compliant, high slew, w/ pull-up resistor
GLMX33PH	3.3 Volt CMOS input levels, PCI compliant, high slew

GLMXLx

This component is supported by APA family.

• Function: Two bi-directional IO pads (global and regular), multiplexed, w/ active low enable
• Input: DE1, D1, PAD1, DE2, D2, PAD2, EN
• Output: PAD1, Y1, PAD2, Y2, GL

Table 18-262. Truth Table

Input							Output
DE1	D1	PAD1	DE2	D2	PAD2	EN	PAD1	Y1	PAD2	Y2	GL
1	X	N/A	1	X	N/A	0	D1	D1	D2	D2	D2
1	X	N/A	1	X	N/A	1	D1	D1	D2	D2	D1
0	X	X	0	X	X	0	N/A	PAD1	N/A	PAD2	PAD2
0	X	X	0	X	X	1	N/A	PAD1	N/A	PAD2	PAD1
1	X	N/A	0	X	X	0	D1	D1	N/A	PAD2	PAD2
1	X	N/A	0	X	X	1	D1	D1	N/A	PAD2	D1
0	X	X	1	X	N/A	0	N/A	PAD1	D2	D2	D2
0	X	X	1	X	N/A	1	N/A	PAD1	D2	D2	PAD1

Table 18-263. Tile Usage

Family	I/O Tiles
All listed	3

Table 18-264. Available GLMIOBLx Macro Types

Name	Description
GLMX25LPLU	2.5 Volt CMOS input levels, low power, low strength, low slew, w/ pull-up resistor
GLMX25LPL	2.5 Volt CMOS input levels, low power, low strength, low slew
GLMX25LPNU	2.5 Volt CMOS input levels, low power, low strength, normal slew, w/ pull-up resistor
GLMX25LPN	2.5 Volt CMOS input levels, low power, low strength, normal slew
GLMX25LPHU	2.5 Volt CMOS input levels, low power, low strength, high slew, w/ pull-up resistor
GLMX25LPH	2.5 Volt CMOS input levels, low power, low strength, high slew
GLMX25LPHLU	2.5 Volt CMOS input levels, low power, high strength, low slew, w/ pull-up resistor
GLMX25LPHL	2.5 Volt CMOS input levels, low power, high strength, low slew
GLMX25LPHNU	2.5 Volt CMOS input levels, low power, high strength, normal slew, w/ pull-up resistor
GLMX25LPHN	2.5 Volt CMOS input levels, low power, high strength, normal slew
GLMX25LPHHU	2.5 Volt CMOS input levels, low power, high strength, high slew, w/ pull-up resistor
GLMX25LPHH	2.5 Volt CMOS input levels, low power, high strength, high slew
GLMX33LLU	3.3 Volt CMOS input levels, low power, low slew, w/ pull-up resistor
GLMX33LL	3.3 Volt CMOS input levels, low power, low slew
GLMX33LNU	3.3 Volt CMOS input levels, low power, normal slew, w/ pull-up resistor
GLMX33LN	3.3 Volt CMOS input levels, low power, normal slew
GLMX33LHU	3.3 Volt CMOS input levels, low power, high slew, w/ pull-up resistor
GLMX33LH	3.3 Volt CMOS input levels, low power, high slew
GLMX33PLU	3.3 Volt CMOS input levels, PCI compliant, low slew, w/ pull-up resistor
GLMX33PL	3.3 Volt CMOS input levels, PCI compliant, low slew
GLMX33PNU	3.3 Volt CMOS input levels, PCI compliant, normal slew, w/ pull-up resistor
GLMX33PN	3.3 Volt CMOS input levels, PCI compliant, normal slew
GLMX33PHU	3.3 Volt CMOS input levels, PCI compliant, high slew, w/ pull-up resistor
GLMX33PH	3.3 Volt CMOS input levels, PCI compliant, high slew

GLPE

This component is supported by APA family.

• Function: LVPECL inputs for high-speed signaling. The GLPE macro reads the difference between the PECLIN and PECLREF analog signals and returns a voltage of 1 if it is above a user-specified threshold.
• Input: PECLIN, PECLREF
• Output: GL

Table 18-265. Truth Table

Inputa		Output
PECLIN	PECLREF	GL
X	X	PECLIN

Note: a. This table describes digital model behavior for PECLIN and PECLREF.

Table 18-266. Tile Usage

Family	I/O Tiles
All listed	1

GLPEMIB

This component is supported by APA family.

• Function: LVPECL inputs for high-speed signaling. The GLPEMIB macro reads the difference between the PECLIN and PECLREF analog signals and returns a voltage of 1 if it is above a user-specified threshold.
• Input: A, EN, PECLIN, PECLREF
• Output: Y, GL

Table 18-267. Truth Table

Inputa			Output
A	EN	PECLIN/PECLREF	GL	Y
X	1	X	PECLIN/PECLREF	PECLIN/PECLREF
X	0	X	A	PECLIN/PECLREF

Note: a. This table describes digital model behavior for PECLIN and PECLREF.

Table 18-268. Tile Usage

Family	I/O Tiles
All listed	1