Combinational truth tables use the following symbols:
- 1 - indicates logic level one
- 0 - indicates logic level zero
- ↑ - indicates positive (rising) edge
- ↓ - indicates negative (falling) edge
- D - indicates input port
- !D - indicates inverted input port
- Q - indicates output port
- QBAR - indicates inverted output port
- X - indicates either logic level one or
zero (don’t care)
DFF
This component is supported by A500K, APA.
Figure 18-48. DFF Logic Diagram
- Function: Positive Edge Triggered D-Type
Flip-Flop.
- Input: D, CLK
- Output: Q
Table 18-91. Truth Table| CLK | Qn+1 |
|---|
| ↑ | D |
Table 18-92. Tile Usage| Family | Tiles |
|---|
| All listed | 1 |
DFFB
This component is supported by DFFB A500K, APA.
Figure 18-49. DFFB Logic Diagram
- Function: Positive Edge Triggered D-Type
Flip-Flop with Active High Set and Clear.
- Input: CLR, SET, CLK, D
- Output: Q
Table 18-93. Truth Table| CLK | SET | CLR | Qn+1 |
|---|
| X | 1 | 0 | 1 |
| X | X | 1 | 0 |
| ↑ | 0 | 0 | D |
Table 18-94. Tile Usage| Family | Tiles |
|---|
| All listed | 1 |
DFFBI
This component is supported by A500K, APA.
Figure 18-50. DFFBI Logic Diagram
- Function: Positive Edge Triggered D-Type
Flip-Flop with Active High Set and Clear and Active Low Output.
- Input: CLR, SET, CLK, D
- Output: QBAR
Table 18-95. Truth Table| CLK | SET | CLR | QBARn+1 |
|---|
| X | 1 | 0 | 0 |
| X | X | 1 | 1 |
| ↑ | 0 | 0 | !D |
Table 18-96. Tile Usage| Family | Tiles |
|---|
| All listed | 4 |
DFFC
This component is supported by A500K, APA.
Figure 18-51. DFFC Logic Diagram
- Function: Positive Edge Triggered D-Type
Flip-Flop with Active High Clear.
- Input: CLR, CLK, D
- Output: Q
Table 18-97. Truth Table| CLK | CLR | Qn+1 |
|---|
| X | 1 | 0 |
| ↑ | 0 | D |
Table 18-98. Tile Usage| Family | Tiles |
|---|
| All listed | 1 |
DFFCI
This component is supported by A500K, APA.
Figure 18-52. DFFCI Logic Diagram
- Function: Positive Edge Triggered D-Type
Flip-Flop with Active High Clear and Active Low Output.
- Input: CLR, CLK, D
- Output: QBAR
Table 18-99. Truth Table| CLK | CLR | QBARn+1 |
|---|
| X | 1 | 0 |
| ↑ | 0 | !D |
Table 18-100. Tile Usage| Family | Tiles |
|---|
| All listed | 1 |
DFFI
This component is supported by A500K, APA.
Figure 18-53. DFFI Logic Diagram
- Function: Positive Edge Triggered D-Type
Flip-Flop with Active Low Output.
- Input: CLK, D
- Output: QBAR
Table 18-101. Truth Table| CLK | QBARn+1 |
|---|
| ↑ | !D |
Table 18-102. Tile Usage| Family | Tiles |
|---|
| All listed | 1 |
DFFL
This component is supported by A500K, APA.
Figure 18-54. DFFL Logic Diagram
- Function: Negative Edge Triggered D-Type
Flip-Flop.
- Input: CLK, D
- Output: Q
Table 18-103. Truth Table| CLK | Qn+1 |
|---|
| ↑ | !D |
Table 18-104. Tile Usage| Family | Tiles |
|---|
| All listed | 1 |
DFFLB
This component is supported by A500K, APA.
Figure 18-55. DFFLB Logic Diagram
- Function: Negative Edge Triggered D-Type
Flip-Flop with Active High Set and Clear.
- Input: CLR, SET, CLK, D
- Output: Q
Table 18-105. Truth Table| CLK | SET | CLR | Qn+1 |
|---|
| X | 1 | 0 | 1 |
| X | X | 1 | 0 |
| ↓ | 0 | 0 | D |
Table 18-106. Tile Usage| Family | Tiles |
|---|
| All listed | 4 |
DFFLBI
This component is supported by A500K, APA.
Figure 18-56. DFFLBI Logic Diagram
- Function: Negative Edge Triggered D-Type Flip-Flop with Active High Set and Clear and
Active Low Output.
- Input: CLR, SET, CLK, D
- Output: Q
Table 18-107. Truth Table| CLK | SET | CLR | Qn+1 |
|---|
| X | 1 | 0 | 1 |
| X | X | 1 | 0 |
| ↓ | 0 | 0 | D |
Table 18-108. Tile Usage| Family | Tiles |
|---|
| All listed | 4 |
DFFLC
This component is supported by A500K, APA.
Figure 18-57. DFFLC Logic Diagram
- Function: Negative Edge Triggered D-Type Flip-Flop with Active High Clear.
- Input: CLR, SET, CLK, D
- Output: Q
Table 18-109. Truth Table| CLK | SET | CLR | Qn+1 |
|---|
| X | 1 | 0 | 1 |
| X | X | 1 | 0 |
| ↓ | 0 | 0 | D |
Table 18-110. Tile Usage| Family | Tiles |
|---|
| All listed | 4 |
DFFLCI
This component is supported by A500K, APA.
Figure 18-58. DFFLCI Logic Diagram
- Function: Negative Edge Triggered D-Type Flip-Flop with Active High Clear and Active Low
Output.
- Input: CLR, CLK, D
- Output: QBAR
Table 18-111. Truth Table| CLK | CLR | QBARn+1 |
|---|
| X | 1 | 1 |
| ↓ | 0 | D |
Table 18-112. Tile Usage| Family | Tiles |
|---|
| All listed | 1 |
DFFLI
This component is supported by A500K, APA.
Figure 18-59. DFFLI Logic Diagram
- Function: Negative Edge Triggered D-Type Flip-Flop with Active Low Output.
- Input: CLK, D
- Output: QBAR
Table 18-113. Truth Table| CLK | QBARn+1 |
|---|
| ↓ | !D |
Table 18-114. Tile Usage| Family | Tiles |
|---|
| All listed | 1 |
DFFLS
This component is supported by A500K, APA.
Figure 18-60. DFFLS Logic Diagram
- Function: Negative Edge Triggered D-Type Flip-Flop with Active High Set.
- Input: SET, CLK, D
- Output: Q
Table 18-115. Truth Table| CLK | SET | Qn+1 |
|---|
| X | 1 | 1 |
| ↓ | 0 | D |
Table 18-116. Tile Usage| Family | Tiles |
|---|
| All listed | 1 |
DFFLSI
This component is supported by A500K, APA.
Figure 18-61. DFFLSI Logic Diagram
- Function: Negative Edge Triggered D-Type Flip-Flop with Active High Set and Active Low
Output.
- Input: SET, CLK, D
- Output: QBAR
Table 18-117. Truth Table| CLK | SET | QBARn+1 |
|---|
| X | 1 | 0 |
| ↓ | 0 | !D |
Table 18-118. Tile Usage| Family | Tiles |
|---|
| All listed | 1 |
DFFS
This component is supported by A500K, APA.
Figure 18-62. DFFS Logic Diagram
- Function: Positive Edge Triggered D-Type Flip-Flop with Active High Set.
- Input: SET, CLK, D
- Output: Q
Table 18-119. Truth Table| CLK | SET | Qn+1 |
|---|
| X | 1 | 0 |
| ↓ | 0 | D |
Table 18-120. Tile Usage| Family | Tiles |
|---|
| All listed | 1 |
DFFSI
This component is supported by A500K, APA.
Figure 18-63. DFFSI Logic Diagram
- Function: Positive Edge Triggered D-Type Flip-Flop with Active High Set and Active Low
Output.
- Input: SET, CLK, D
- Output: QBAR
Table 18-121. Truth Table| CLK | SET | QBARn+1 |
|---|
| X | 1 | 0 |
| ↓ | 0 | !D |
Table 18-122. Tile Usage| Family | Tiles |
|---|
| All listed | 1 |
LD
This component is supported by A500K, APA.
Figure 18-64. LD Logic Diagram
- Function: Active High Latch.
- Input: EN, D
- Output: Q
Table 18-123. Truth Table| EN | Qn+1 |
|---|
| 0 | Q |
| 1 | D |
Table 18-124. Tile Usage| Family | Tiles |
|---|
| All listed | 1 |
LDB
This component is supported by A500K, APA.
Figure 18-65. LDB Logic Diagram
- Function: Active High Latch with Active
High Set and Clear.
- Input: CLR, SET, EN, D
- Output: Q
Table 18-125. Truth Table| EN | SET | CLR | Qn+1 |
|---|
| X | 1 | 0 | 1 |
| X | X | 1 | 0 |
| 1 | 0 | 0 | D |
| 0 | 0 | 0 | Q |
Table 18-126. Tile Usage| Family | Tiles |
|---|
| All listed | 2 |
LDBI
This component is supported by A500K, APA.
Figure 18-66. LDBI Logic Diagram
- Function: Active High Latch with Active High Set and Clear and Active Low Output.
- Input: CLR, SET, EN, D
- Output: QBAR
Table 18-127. Truth Table| EN | SET | CLR | QBARn+1 |
|---|
| X | 1 | 0 | 0 |
| X | X | 1 | 1 |
| 1 | 0 | 0 | !D |
| 0 | 0 | 0 | QBAR |
Table 18-128. Tile Usage| Family | Tiles |
|---|
| All listed | 2 |
LDC
This component is supported by A500K, APA.
Figure 18-67. LDC Logic Diagram
- Function: Active High Latch with Active High Clear.
- Input: CLR, EN, D
- Output: Q
Table 18-129. Truth Table| EN | CLR | Qn+1 |
|---|
| X | 0 | 0 |
| 1 | 0 | D |
| 0 | 0 | Q |
Table 18-130. Tile Usage| Family | Tiles |
|---|
| All listed | 1 |
LDCI
This component is supported by A500K, APA.
Figure 18-68. LDCI Logic Diagram
- Function: Active High Latch with Active High Clear and Active Low Output.
- Input: CLR, EN, D
- Output: QBAR
Table 18-131. Truth Table| EN | CLR | QBARn+1 |
|---|
| X | 1 | 1 |
| 1 | 0 | !D |
| 0 | 0 | QBAR |
Table 18-132. Tile Usage| Family | Tiles |
|---|
| All listed | 1 |
LDI
This component is supported by A500K, APA.
Figure 18-69. LDI Logic Diagram
- Function: Active High Latch with Active High Clear and Active Low Output.
- Input: EN, D
- Output: QBAR
Table 18-133. Truth Table| EN | QBARn+1 |
|---|
| 0 | QBAR |
| 1 | !D |
Table 18-134. Tile Usage| Family | Tiles |
|---|
| All listed | 1 |
LDL
This component is supported by A500K, APA.
Figure 18-70. LDL Logic Diagram
- Function: Active High Latch.
- Input: EN, D
- Output: Q
Table 18-135. Truth Table| EN | Qn+1 |
|---|
| 0 | D |
| 1 | Q |
Table 18-136. Tile Usage| Family | Tiles |
|---|
| All listed | 1 |
LDLB
This component is supported by A500K, APA.
Figure 18-71. LDLB Logic Diagram
- Function: Active Low Latch with Active High Set and Clear.
- Input: CLR, SET, EN, D
- Output: Q
Table 18-137. Truth Table| EN | SET | CLR | Qn+1 |
|---|
| X | 1 | 0 | 1 |
| X | X | 1 | 1 |
| 1 | 0 | 0 | D |
| 0 | 0 | 0 | Q |
Table 18-138. Tile Usage| Family | Tiles |
|---|
| All listed | 2 |
LDLBI
This component is supported by A500K, APA.
Figure 18-72. LDLBI Logic Diagram
- Function: Active Low Latch with Active High Set and Clear.
- Input: CLR, SET, EN, D
- Output: QBAR
Table 18-139. Truth Table| EN | SET | CLR | QBARn+1 |
|---|
| X | 1 | 0 | 0 |
| X | X | 1 | 1 |
| 1 | 0 | 0 | !D |
| 0 | 0 | 0 | QBAR |
Table 18-140. Tile Usage| Family | Tiles |
|---|
| All listed | 2 |
LDLC
This component is supported by A500K, APA.
Figure 18-73. LDLC Logic Diagram
- Function: Active Low Latch with Active High Clear.
- Input: CLR, EN, D
- Output: Q
Table 18-141. Truth Table| EN | CLR | Qn+1 |
|---|
| X | 1 | 0 |
| 0 | 0 | D |
| 1 | 0 | Q |
LDLCI
This component is supported by A500K, APA.
Figure 18-74. LDLCI Logic Diagram
- Function: Active Low Latch with Active High Clear and Active Low Output.
- Input: CLR, EN, D
- Output: QBAR
Table 18-142. Truth Table| EN | CLR | QBARn+1 |
|---|
| X | 1 | 1 |
| 1 | 0 | !D |
| 0 | 0 | QBAR |
Table 18-143. Tile Usage| Family | Tiles |
|---|
| All listed | 1 |
LDLI
This component is supported by A500K, APA.
Figure 18-75. LDLI Logic Diagram
- Function: Active Low Latch with Active Low Output.
- Input: EN, D
- Output: QBAR
Table 18-144. Truth Table| EN | QBARn+1 |
|---|
| 0 | !D |
| 1 | QBAR |
Table 18-145. Tile Usage| Family | Tiles |
|---|
| All listed | 1 |
LDLS
This component is supported by A500K, APA.
Figure 18-76. LDLS Logic Diagram
- Function: Active Low Latch with Active High Set.
- Input: SET, EN, D
- Output: Q
Table 18-146. Truth Table| EN | CLR | Qn+1 |
|---|
| X | 1 | 1 |
| 0 | 0 | D |
| 1 | 0 | Q |
Table 18-147. Tile Usage| Family | Tiles |
|---|
| All listed | 1 |
LDLSI
This component is supported by A500K, APA.
Figure 18-77. LDLSI Logic Diagram
- Function: Active Low Latch with Active High Set and Active Low Output.
- Input: SET, EN, D
- Output: QBAR
Table 18-148. Truth Table| EN | CLR | QBARn+1 |
|---|
| X | 1 | 0 |
| 0 | 0 | !D |
| 1 | 0 | QBAR |
Table 18-149. Tile Usage| Family | Tiles |
|---|
| All listed | 1 |
LDS
This component is supported by A500K, APA.
Figure 18-78. LDS Logic Diagram
- Function: Active High Latch with Active High Set.
- Input: SET, EN, D
- Output: Q
Table 18-150. Truth Table| EN | SET | Qn+1 |
|---|
| X | 1 | 1 |
| 0 | 0 | Q |
| 1 | 0 | D |
Table 18-151. Tile Usage| Family | Tiles |
|---|
| All listed | 1 |
LDSI
This component is supported by A500K, APA.
Figure 18-79. LDSI Logic Diagram
- Function: Active High Latch with Active High Set and Active Low Output.
- Input: SET, EN, D
- Output: QBAR
Table 18-152. Truth Table| EN | SET | QBARn+1 |
|---|
| X | 1 | 0 |
| 0 | 0 | QBAR |
| 1 | 0 | !D |
Table 18-153. Tile Usage| Family | Tiles |
|---|
| All listed | 1 |
