7.5.2 Timing Simulation

ViewSim timing simulation is no longer supported by Actel since the Innoveda back-annotate feature is not available in Actel Designer software anymore. To perform timing simulation:

1. Export a VHDL or Verilog netlist and *.sdf file from Actel Designer software.
2. Use the HDL netlist and *.sdf file to run timing simulation in other HDL based simulators.