3.6.2.2.4 SFRP – Support
FIFO Read Pointer Register
Name:
SFRP
Offset:
0x0DE
Reset:
0x00
Bit
7
6
5
4
3
2
1
0
SFRP[4:0]
Access
R
R
R
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit 7 – Reserved
Bit
This bit is reserved and
always returns ‘0’ when read.
Bit 6 – Reserved
Bit
This bit is reserved and
always returns ‘0’ when read.
Bit 5 – Reserved Bit
This bit is reserved and
always returns ‘0’ when read.
Bits 4:0 – SFRP[4:0] Support FIFO Read
Pointer Register
This register gives read and
write access to the support FIFO read pointer (RdPtr). The manipulation of the RdPtr
requires thorough knowledge of the internal functionality of the FIFO. To avoid
unpredictable behavior, the RdPtr must only be changed in IDLEMode. The RdPtr can
have values between 0 and 31. The pointer cycles through these values in a round
robin manner. The difference between WrPtr and RdPtr (WrPtr – RdPtr) must never
exceed 16, because otherwise the FIFO will be in an undefined state. This can be
checked by reading the fill level in the SFL.SFFLS register. If the value is larger
than 16, the RdPtr or WrPtr value is invalid. Writing to this register overrides any
other access.
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