3.6.2.2.2 SFI – Support
FIFO Interrupt Mask Register
| Name: | SFI |
| Offset: | 0x0E0 |
| Reset: | 0x00 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| | | | | | | | SFERIM | SFFLIM | |
| Access | R | R | R | R | R | R | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bit 7 – Reserved
Bit
This bit is reserved and
always returns ‘0’ when read.
Bit 6 – Reserved
Bit
This bit is reserved and
always returns ‘0’ when read.
Bit 5 – Reserved Bit
This bit is reserved and
always returns ‘0’ when read.
Bit 4 – Reserved Bit
This bit is reserved and
always returns ‘0’ when read.
Bit 3 – Reserved Bit
This bit is reserved and
always returns ‘0’ when read.
Bit 2 – Reserved Bit
This bit is reserved and
always returns ‘0’ when read.
Bit 1 – SFERIM Support FIFO Error
Interrupt Mask
Writing this bit to
‘1’ enables the error interrupt. An interrupt is generated if a
FIFO overflow or underflow occurs or if read and write pointer are set to invalid
addresses.
Bit 0 – SFFLIM Support FIFO Fill Level Interrupt Mask
Writing this bit to
‘1’ enables the fill level interrupt. Precise conditions for
this event are described at the SFS.SFFLRF bit.
