3.6.2.2.1 SFC – Support FIFO Configuration Register
| Name: | SFC |
| Offset: | 0x0E1 |
| Reset: | 0x00 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| SFDRA | SFFLC[4:0] | ||||||||
| Access | R/W | R | R | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bit 7 – SFDRA Support FIFO Direct Read Access Operational Mode
| SFDRA | Description |
|---|---|
0 | Direct write access: The FIFO is configured for data reception and serves as RSSI value storage. The AVR® can only read from the FIFO. Write access is allowed via the direct write access interface from the RSSI buffer. |
1 | Direct read access: The FIFO is configured for data transmission. The AVR can only write to the FIFO. Read access is allowed via the direct read access interface from the TX modulator. |
Bit 6 – Reserved Bit
0’ when read.Bit 5 – Reserved Bit
0’ when read.