Writing a ‘1’
to this bit location clears the support FIFO. RdPtr, WrPtr and fill level are reset
to ‘0’. The support FIFO status register is cleared. The support
FIFO configuration registers (SFC and SFI) keep their settings. The data content of
the FIFO is also retained. It can be recovered by RdPtr and WrPtr manipulations.
Reading this bit always returns ‘0’.
Bit 6 – Reserved
Bit
This bit is reserved and
always returns ‘0’ when read.
Bit 5 – Reserved
Bit
This bit is reserved and
always returns ‘0’ when read.
Bits 4:0 – SFFLS[4:0] Support FIFO Fill
Level Status
The current fill level of the
support FIFO is stored in SFFLS. These bits are read-only. An SFFLS value that is
larger than 16 indicates incorrect programming of the read (SFRP) or write (SFWP)
pointer. The fill level is updated one system clock cycle after a read/write access
or pointer manipulation.
The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.
