3.6.2.2.7 Support FIFO
Status Register
| Name: | SFS |
| Offset: | 0x0DB |
| Reset: | 0x00 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| | | | | | | SFOFL | SFUFL | SFFLRF | |
| Access | R | R | R | R | R | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bit 7 – Reserved
Bit
This bit is reserved and
always returns ‘0’ when read.
Bit 6 – Reserved
Bit
This bit is reserved and
always returns ‘0’ when read.
Bit 5 – Reserved Bit
This bit is reserved and
always returns ‘0’ when read.
Bit 4 – Reserved
Bit
This bit is reserved and
always returns ‘0’ when read.
Bit 3 – Reserved Bit
This bit is reserved and
always returns ‘0’ when read.
Bit 2 – SFOFL Support FIFO
Overflow Flag
This error flag bit is set if
there is a write access to a full FIFO or if the fill level exceeds the FIFO depth,
which can happen due to faulty pointer manipulations in the SFRP or SFWP registers.
The SFOFL flag can generate an interrupt when masked in SFI.SFERIM. The SFOFL flag
is automatically cleared when the interrupt is executed or by writing a
‘1’ to its bit location.
Bit 1 – SFUFL Support FIFO Underflow Flag
This error flag bit is set if
there is a read access to an empty FIFO. The SFUFL flag can generate an interrupt
when masked in SFI.SFERIM. The SFUFL flag is automatically cleared when the
interrupt is executed or by writing a ‘1’ to its bit
location.
Bit 0 – SFFLRF Support FIFO Fill Level Reached Status
Flag
- If SFC.SFDRA =
0, this flag is set if the current fill level of the
support FIFO matches the fill level configuration (SFC.SFFLC) after the
reception of a byte.
- If SFC.SFDRA =
1, this flag is set if the current fill level of the
support FIFO matches the fill level configuration (SFC.SFFLC) after the
transmission of a byte.
- The SFFLRF flag generates an
interrupt when masked in SFI.SFFLIM. The SFFLRF flag is automatically
cleared when the interrupt is executed or by writing a ‘
1’
to its bit location.
