2.7.3.1 Support FIFO Processing
The support FIFO (SFIFO) has a depth of 16 bytes and can be used to hold the desync and
preamble parts of a telegram. Data can be written to the SFIFO by using the “Write TX Preamble
FIFO” SPI command. (For more information, see Write TX Preamble FIFO.) If a byte is written to a full FIFO,
the event flag SYS_ERR is raised in the events.system event byte unless the
eepTrxConf.sysConfig.SFIFO_OFL_UFL_RX_disable EEPROM variable is set to
‘1’.
| Address | Name | Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
|---|---|---|---|---|---|---|---|---|---|
| 0x0017 | sysConfig | — | — | VS22V | VS5V | SFIFO_OFL_UFL_RX_disable | DFIFO_OFL_UFL_RX_disable | AVCCdisable | LOWBATTdisable |
If the SFIFO depth is not sufficient to store the entire preamble, it can be refilled during operation. An event is available to indicate to an external host that the fill level of the SFIFO reached a certain threshold. At this point, the host can write additional data to the SFIFO.
The fill level threshold can be configured independently for path A and path B of each service in the eepServices.txPreambleSysEventx.PreambleBufFillLevelx[4:0] EEPROM variable. The event flag SFIFO (bit 2) in the events.system event byte is set each time the fill level reaches the configured threshold. In addition, the EVENT pin is triggered if the eepServices.txPreambleSysEventx.txPreambleBufEvMaskx EEPROM variable is set.
| Address Service0 | Name | Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
|---|---|---|---|---|---|---|---|---|---|
| 0x0107 | txPreambleSysEventA | — | — | txPreambleBufEvMaskA | PreambleBufFillLevelA[4:0] | ||||
| 0x0108 | txPreambleSysEventB | — | — | txPreambleBufEvMaskB | PreambleBufFillLevelB[4:0] | ||||
The current fill level of the SFIFO can be read at any time by using the “Read Fill Level RSSI FIFO” SPI command. It is not possible to read data from the SFIFO in TXMode.
If the data polarity in the eepServices.TMCR2x.TMPOL variable is set to ‘1’,
the data in the SFIFO is inverted before it is transmitted (see Data Polarity).
Data Structure
There are command and data bytes that must be written to the FIFO in a special arrangement. The organization of the SFIFO is symbol-based and MSB-first.
Every pattern sequence starts with a command byte. The command contains the following information:
- Bit 7 defines the transmission mode:
0= single mode1= repeat mode
- Bits 6..0 contain the number of symbols of the pattern sequence
Single Mode
In single mode, a data pattern length of up to 127 symbols is allowed. The data pattern is stored in the bytes that follow after the command byte. The data bytes must correspond to the configured number of symbols. The rest of a final incomplete byte is discarded.
Repeat Mode
In repeat mode, a data pattern of up to 32 symbols can be repeated up to 255 times. Two command bytes are used for the repeat mode as follows:
- Command Byte 0:
- Bit 7 must be set to
‘
1’ to mark the repeat mode - Bits 6..0 contain the number of symbols of the data pattern sequence in a range of 1..32 symbols
- Bit 7 must be set to
‘
- Command Byte 1:
- Bits 7..0 define the number of repetitions of the data pattern in a range of 1..255 repetitions
The data pattern is stored in the (up to four) bytes that follow the command bytes. The data bytes must correspond to the configured number of symbols in the repeat pattern. The rest of a final incomplete byte is always discarded.
