3.11.3.1 Power ON and Brown-Out Reset (POR)

The DVCC supply voltage regulator output is monitored permanently by the brown-out detector (BOD). This monitor circuit is also used during the power-up sequence. After a PWRON or NPWRONx edge event, the DVCC voltage ramps up. When reaching the V_BOT+ voltage (DVCC reset level, typically 1.27V), the internal reset switches to ‘1’ and an internal timer is started. The time depends on the reset source, as described in Table 3-119 in more detail. After the time period of t_TOUT, the negative edge of the internal reset starts the AVR operation. The complete power-up timing is shown in Figure 3-106.

Figure 3-100. AVR Power-Up with PWRON and NRESET

Figure 3-101. AVR Power-Up with NPWRON and NRESET

The duration of the internal reset delay, t_TOUT, can be extended by an external signal applied to the NRESET pin. The DVCC voltage must already be stable. If the signal at NRESET reaches the voltage level V_RST (approximately VS/2), the reset timer, t_TOUT, is re-triggered to cause the internal reset.

Figure 3-102. AVR Power-Up with Externally Extended Reset

A reset is generated when DVCC voltage drops below the internal threshold level (V_BOT-, typically 1.25V). If the DVCC voltage increases again (V_BOT+ , typically 1.27V, 20 mV hysteresis) after the time period of t_TOUT, the AVR system resumes operation. The timing is described in AVR Reset Timing. A typical DVCC voltage drop scenario displays in the following figure.

Figure 3-103. DVCC Drop during Operation