3.11.3.4 AVR Reset Timing
When an AVR reset source becomes active, the AVR registers are reset. The operation is started again at the next rising edge of the selected clock source. After all reset sources become inactive, a delay counter is invoked, which extends the internal reset by tTOUT. This method allows all supplies to reach a stable level before normal operation can be started. The time-out period is determined by the EXTCLKEN fuse, RSTDISABLE fuse and DWEN fuse.
The table below calculates the time, tTOUT, until the internal reset is removed. This time is dependent on the clock source chosen, which is either CLKFRC (internal fast RC oscillator) or CLKEXT (external oscillator, which can be applied at pin PC1).
|
Reset Source |
EXTCLKEN Fuse |
RSTDISABLE Fuse |
DWEN Fuse |
tTOUT in Numbers of Clocks |
|---|---|---|---|---|
|
POR |
1 |
1 |
1 |
142 x CLKFRC |
|
POR |
1 |
1 |
0 |
512 x CLKSRC + 140 x CLKFRC |
|
POR |
1 |
0 |
1 |
512 x CLKSRC + 140 x CLKFRC |
|
POR |
1 |
0 |
0 |
512 x CLKSRC + 140 x CLKFRC |
|
POR |
0 |
1 |
1 |
141 x CLKEXT |
|
POR |
0 |
1 |
0 |
141 x CLKEXT |
|
POR |
0 |
0 |
1 |
141 x CLKEXT |
|
POR |
0 |
0 |
0 |
141 x CLKEXT |
|
NRESET |
1 |
1 |
1 |
140 x CLKFRC |
|
NRESET |
1 |
1 |
0 |
Not possible, NRESET is disabled |
|
NRESET |
1 |
0 |
1 |
Not possible, NRESET is disabled |
|
NRESET |
1 |
0 |
0 |
Not possible, NRESET is disabled |
|
NRESET |
0 |
1 |
1 |
141 x CLKEXT |
|
NRESET |
0 |
1 |
0 |
Not possible, NRESET is disabled |
|
NRESET |
0 |
0 |
1 |
Not possible, NRESET is disabled |
|
NRESET |
0 |
0 |
0 |
Not possible, NRESET is disabled |
|
WDTRESET |
1 |
1 |
1 |
512 x CLKSRC + 140 x CLKFRC |
|
WDTRESET |
1 |
1 |
0 |
512 x CLKSRC + 140 x CLKFRC |
|
WDTRESET |
1 |
0 |
1 |
512 x CLKSRC + 140 x CLKFRC |
|
WDTRESET |
1 |
0 |
0 |
512 x CLKSRC + 140 x CLKFRC |
|
WDTRESET |
0 |
1 |
1 |
512 x CLKSRC + 140 x CLKEXT |
|
WDTRESET |
0 |
1 |
0 |
512 x CLKSRC + 140 x CLKEXT |
|
WDTRESET |
0 |
0 |
1 |
512 x CLKSRC + 140 x CLKEXT |
|
WDTRESET |
0 |
0 |
0 |
512 x CLKSRC + 140 x CLKEXT |
The following figure illustrates a typical power-up sequence. The power supply domain of the circuit delivering the signal is included in brackets.
- The main supply is applied to the VS pin. The internal supply generators remain disabled. The DVCC_OK = LOW indicates that the DVCC is not yet active and therefore not high enough for operation.
- The PWRON pin is set to high or an NPWRON pin is pulled to low (button pressed). This triggers the port_wake signal, enabling the DVCC regulator.
- When the DVCC voltage rises above the reset threshold VBOT+, the DVCC_OK signal switches to high, indicating a valid operation voltage. An analog delay tRST_DVCC_min is implemented to ensure enough settling time for all signals.
- The DVCC reset (RST_DVCC) is set as early as possible with the rising DVCC voltage and cleared by the high level of DVCC_OK.
- The RST_DVCC signal triggers the signal INTERNAL_RESET. The internal AVR reset is extended by a reset state machine that clears the registers and loads the calibration settings of all regulators, reset monitors and RC oscillators. The CAL_RDY signal is set to high after the calibration data is available to the power management circuit.
- The internal AVR reset is released after reset and calibration data of voltage regulators, reset levels and RC oscillators are available. The AVR firmware starts operation. The ports are configured according to the EEPROM settings. The PORT_RDY signal activates the port configuration.