3.11.3 AVR Reset

During AVR reset, all I/O registers are set to their initial (hardware-defined) values and the AVR program starts execution from the reset vector. The following circuit diagram shows the reset logic of the ATA8510/15.

Three sources can generate an AVR reset:

  • DVCC-related power on reset (POR):

    The AVR reset is generated when the supply voltage DVCC is below the brown-out reset threshold (VBOT-). The brown-out detector is always enabled.

  • External reset (EXTR):

    The AVR reset is generated when a low level is detected on the NRESET pin for longer than 10 µs.

  • Watchdog reset (WDR):

    The AVR reset is generated when the watchdog is enabled and its timer period expires.

Note: The RF front end and XTO has a separate reset circuit monitoring the AVCC voltage. See Voltage Monitor (Low Battery Indicator) for more details..
Figure 3-99. Reset Logic of the ATA8510/15