2.8.7.5 Receive CRC Checker

The ATA8510/15 implements a highly configurable hardware CRC checker for the received data payload. The CRC checker can be activated independently for path A and path B of each service in the eepServices.RXBC1.RXCEx variables.

If enabled, all bits that are received after the SOT event are transferred to the CRC checker with the option to skip up to 255 bits at the beginning.

The success of the CRC check is stored in the TESRA.CRCOA hardware register bit for path A and TESRB.CRCOB for path B until the next receiver start-up or path restart. The bits can be read with the “Read SRAM Register” SPI command from address 0x096 and 0x095 for path A and path B, respectively. If CRCOx is ‘1’, the CRC check was successful for the corresponding path.

The usage of the receive CRC checker is bound to the following conditions:

• The CRC checker is available only in buffered receive mode and not in transparent receive mode.
• The data payload of the telegram must be concluded by a well-defined code violation to keep arbitrary bits at the end of the telegram from disturbing the checksum. Ideally, the telegram length EOT condition (see Telegram Length) is used to define the number of received data bits.

The CRC checker cannot be used if the “Stay in RX after EOT” option is set (eepServices.rxSetPathx[1].RXTEHx = 1) because the checksum is reset at every receiver start-up phase and every path restart (compare Figure 2-24).