3.5.3.2 CRC Calculation

A cyclic redundancy check (CRC) calculation of the payload data can be enabled by setting TMCR2.TMCRCE to ‘1’. The following figure shows a block diagram of the CRC module in 16-bit mode.

The CRC block is implemented as a 16-bit shift register with configurable feedback loops. When the TX modulator is enabled by releasing the corresponding power reduction register, the CRC shift register is initialized with TMCIH/TMCIL (default value: 0x00). The length of the shift register can be reduced to eight bits or four bits in the TMCR2.TMCRCL register for CRC8 or CRC4 calculations, respectively. The corresponding logic is not shown in the preceding figure.

The coefficients of the CRC polynomial can be configured in the TMCPH/L registers. The position in the TMCP word corresponds to the degree of the term within the polynomial as illustrated for a 16-bit polynomial in the following figure. The coefficient of the x⁰ term of a CRC polynomial must always be 1 in, and, therefore, bit 0 of TMCPL is hard-wired to ‘1’.

The TX modulator state machine ensures that only data from the DFIFO are strobed to the CRC module. A skip period can be configured in TMCSB. If this value is greater than 0x00, the state machine omits the first TMCSB bits of the DFIFO before enabling the CRC.

The current CRC result can be read in the TMCRH/L registers. It is appended to the TX data stream after the DFIFO processing is complete.