3.5.3.1 TX Modulator Overview

The TX modulator generates the serial transmission data stream for the TXMode(buffered). The following figure shows a block diagram of the TX modulator hardware.

The data sources of the TX modulator are the support FIFO (SFIFO) and the data FIFO (DFIFO). An internal repetition FIFO is used as a temporary buffer for a repeating pattern during the SFIFO processing.

The data is read byte-wise from the FIFOs, then written to a shift register that generates the serial output, which is synchronized to an accurate asynchronous data rate clock by a single output register. The data rate clock is provided by Timer2 or Timer3, depending on the setting of TMCR1.TMSCS. The corresponding timer must be configured to deliver the symbol rate clock if Manchester coding is activated or the bit rate clock if NRZ coding is activated.

The data at the output of the shift register can optionally be Manchester encoded with selectable polarity. A CRC4/8/16 checksum of the DFIFO content can automatically be attached to the end of the telegram. The generation options of this checksum are highly configurable.

Finally, a stop sequence with a length of up to eight symbols can be added to create a defined Manchester violation. The TX modulator is enabled by setting the PRR2.PRTM power reduction register to ‘0’.

The entire flow is controlled by a finite state machine that is configured and started by firmware.

The main TX modulator settings and their effects are summarized in the following table.