3.5.3.6 Control State Machine

The control of the data flow in the TX modulator is done by a finite state machine (FSM). The FSM starts when the TX modulator is enabled via the appropriate PRR2.PRTM power reduction register and runs to its final state. Then, the transmission complete flag TMSR.TMTCF is raised, triggering an interrupt if masked in TMCR1.TMCIM. The FSM can only be restarted by disabling and enabling the TX modulator again in the power-reduction register.

The TX modulator must be enabled directly before the timer that provides the asynchronous data rate clock is enabled. This ensures one symbol time for initializing the TX modulator, because the timer only provides the first clock pulse after the end of this period.

The AVR IO clock frequency must be at least 15 times larger than the shift clock frequency. The following figure shows the host FSM of the TX modulator.

The FSM starts with the SFIFO processing. If the fill level of the SFIFO is greater than 0, the data is read and processed byte by byte until the SFIFO is empty. The bytes from the SFIFO are interpreted as command and data bytes in a special way that is described in Support FIFO Processing.

The SFIFO processing is succeeded by the DFIFO processing. If the fill level of the DFIFO is greater than 0, the data is read byte by byte and transmitted until the number of bits stored in TMTLH/L is reached. If the TMTLH/L registers are both set to “0x00”, data is transmitted until the DFIFO is empty. A CRC checksum is appended to the data if required as described in CRC Calculation.

The stop sequence processing builds and appends the stop sequence as described in Stop Sequence.

Finally, the end of transmission is performed by resetting the internal control signals and raising the TMSR.TMTCF flag.